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參數(shù)資料
| 型號： | MSM9000B-XXAV-Z-XX |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 16 X 60 DOTS DOT MAT LCD DSPL CTLR, UUC |
| 封裝： | 35 MM, TCP |
| 文件頁數(shù)： | 5/39頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MSM9000B-XXAV-Z-XX |
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Semiconductor
13/39
MSM9000B-xx
FEDL9000B-01
N1
N2
LL
LH
HL
HH
Contrast adjustment range by command
0 to 7
1 to 8
2 to 9
3 to A
TEST (Test Signal)
Test signal input pin provided for test by the manufacturer. Fix this pin to L or leave it open.
SEG1 to SEG60 (Segment 1 to Segment 60)
Segment signal output pins to drive the LCD. Leave the unused pins open.
COM1 to COM16 (Common 1 to Common 16)
Common signal output pins to drive the LCD. When the duty cycle is 1/9, use COM1 to COM9
and leave COM10 to COM16 open.
VDD
Power supply pin to the logic section. Connect this pin to the positive terminal on the power
supply.
VSS
Pin to be connected to the GND power supply.
VSS1, VSS4, VSS5
Pins for voltage multiplier outputs and LCD power supply. Connect capacitors of 0.1
F
between these pins and VDD for the charge distribution with VSS2, 3 capacitor and for voltage
stabilization during generation of LCD bias voltages. The logical values of the LCD bias
voltage are as follows:
Highest voltage: VDD
VSS1=VSS2, 3/2
VSS2, 3
VSS4=VSS2, 3+VSS2, 3/2
Lowest voltage: VSS5=VSS2, 3+VSS2, 3/2+VSS2, 3/2
For both the 1/9 and 1/16 duty, 1/4 bias is used.
VSS2, 3
Voltage regulator output pin & LCD bias generator input used as a reference voltage for the
LCD bias generator.
Connect a capacitor of 0.1
F between this pin and VDD for charge distribution among
capacitors and voltage stabilization during generation of various LCD bias voltages.
VSS6
Pin to connect the capacitor to store the 3-/2-fold voltage. Connect a capacitor of 0.1
F or more
between this pin and VDD.
VSH
Halves output pin for the voltage multiplier(3-/2-fold). Connect a 0.1
F capacitor between
this pin and VDD.
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