參數(shù)資料
型號: MSP430F2617TPN
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP80
封裝: GREEN, PLASTIC, LQFP-80
文件頁數(shù): 62/102頁
文件大?。?/td> 1509K
代理商: MSP430F2617TPN
CVREF+
1 F
0
1 ms
10 ms
100 ms
tREFON
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in F
100 F
10 F
MSP430F261x
MSP430F241x
SLAS541H
– JUNE 2007 – REVISED MAY 2011
12-Bit ADC Built-In Reference
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
NOM
MAX
UNIT
-40
°C to 85°C
2.4
2.5
2.6
REF2_5V = 1 for 2.5 V,
3 V
Positive built-in
IVREF+max ≤ IVREF+ ≤ IVREF+min
105
°C
2.37
2.5
2.64
VREF+
reference voltage
V
-40
°C to 85°C
1.44
1.5
1.56
REF2_5V = 0 for 1.5 V,
output
2.2 V/3 V
IVREF+max ≤ IVREF+ ≤ IVREF+min
105
°C
1.42
1.5
1.57
REF2_5V = 0,
2.2
IVREF+max ≤ IVREF+ ≤ IVREF+min
AVCC minimum
voltage, positive
REF2_5V = 1,
2.8
AVCC(min)
V
built-in reference
-0.5 mA
≤ IVREF+ ≤ IVREF+min
active
REF2_5V = 1,
2.9
-1 mA
≤ IVREF+ ≤ IVREF+min
2.2 V
0.01
-0.5
Load current out of
IVREF+
mA
VREF+terminal
3 V
0.01
-1
IVREF+ = 500 A ± 100 A,
2.2 V
±2
Analog input voltage
≈ 0.75 V,
LSB
Load-current
3 V
±2
REF2_5V = 0
IL(VREF)+
regulation, VREF+
IVREF+ = 500 A ± 100 A,
terminal (1)
Analog input voltage
≈ 1.25 V,
3 V
±2
LSB
REF2_5V = 1
Load current
IVREF+ = 100 A → 900 A,
IDL(VREF) +
regulation, VREF+
CVREF+ = 5 F, ax ≈ 0.5 × VREF+,
3 V
20
ns
terminal (2)
Error of conversion result
≤ 1 LSB
Capacitance at pin
REFON = 1,
CVREF+
2.2 V/3 V
5
10
F
VREF+
(3)
0 mA
≤ IVREF+ ≤ IVREF+max
Temperature
IVREF+ is a constant in the range of
TREF+
coefficient of built-in
2.2 V/3 V
±100
ppm/
°C
0 mA
≤ IVREF+ ≤ 1 mA
reference (2)
Settle time of
internal reference
IVREF+ = 0.5 mA, CVREF+ = 10 F,
tREFON
2.2 V
17
ms
voltage (see
VREF+ = 1.5 V, VAVCC = 2.2 V
Figure 38 ) (4) (2)
(1)
Not production tested, limits characterized.
(2)
Not production tested, limits verified by design.
(3)
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins VREF+ and AVSS and VREF-/VeREF- and AVSS: 10 F tantalum and 100 nF ceramic.
(4)
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
Figure 38. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
62
Copyright
2007–2011, Texas Instruments Incorporated
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