參數(shù)資料
型號： MSP430F2617TPN
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP80
封裝： GREEN, PLASTIC, LQFP-80
文件頁數(shù)： 66/102頁
文件大小： 1509K
代理商： MSP430F2617TPN
Positive
Negative
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
RLoad =
AVCC
CLoad = 100pF
2
DAC Output
MSP430F261x
MSP430F241x
SLAS541H
– JUNE 2007 – REVISED MAY 2011
12-Bit DAC Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Resolution
12-bit monotonic
12
bits
VREF = 1.5 V,
2.2 V
±2.0
±8.0
DAC12AMPx = 7, DAC12IR = 1
INL
Integral nonlinearity(1)
LSB
VREF = 2.5 V,
3 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 1.5 V,
2.2 V
±0.4
±1.0
DAC12AMPx = 7, DAC12IR = 1
DNL
Differential nonlinearity(1)
LSB
VREF = 2.5 V,
3 V
DAC12AMPx = 7, DAC12IR = 1
VREF = 1.5 V,
2.2 V
±21
DAC12AMPx = 7, DAC12IR = 1
Offset voltage without
calibration(1)(2)
VREF = 2.5 V,
3 V
DAC12AMPx = 7, DAC12IR = 1
EO
mV
VREF = 1.5 V,
2.2 V
±2.5
DAC12AMPx = 7, DAC12IR = 1
Offset voltage with
calibration(1)(2)
VREF = 2.5 V,
3 V
DAC12AMPx = 7, DAC12IR = 1
Offset error temperature
dE(O)/dT
2.2 V/3 V
30
V/C
coefficient(3)
VREF = 1.5 V
2.2 V
±3.50
EG
Gain error(3)
% FSR
VREF = 2.5 V
3 V
10
ppm of
dE(G)/dT
Gain temperature coefficient(3)
2.2 V/3 V
FSR/
°C
DAC12AMPx = 2
100
tOffset_Cal
Time for offset calibration(4)
DAC12AMPx = 3, 5
2.2 V/3 V
32
ms
DAC12AMPx = 4, 6, 7
6
(1)
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients
"a" and "b" of
the first-order equation: y = a + b
× x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
(2)
The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
(3)
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients
"a" and "b" of
the first-order equation: y = a + b
× x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
(4)
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx=
{0, 1}. The DAC12 module should be configured prior to initiating calibration. Port activity during calibration may affect accuracy and is
not recommended.
Figure 41. Linearity Test Load Conditions and Gain/Offset Definition
66
Copyright
2007–2011, Texas Instruments Incorporated
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