參數(shù)資料
型號： MSP430F5132IRSBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, RISC MICROCONTROLLER, PQCC40
封裝： GREEN, PLASTIC, WQFN-40
文件頁數(shù)： 33/102頁
文件大小： 1183K
代理商： MSP430F5132IRSBT
MSP430F51x1
MSP430F51x2
SLAS619A
– AUGUST 2010 – REVISED AUGUST 2011
Schmitt-Trigger Inputs
– General Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1.8 V
0.80
1.40
VIT+
Positive-going input threshold voltage
V
3 V
1.50
2.10
1.8 V
0.45
1.00
VIT–
Negative-going input threshold voltage
V
3 V
0.75
1.65
1.8 V
0.3
0.8
Vhys
Input voltage hysteresis (VIT+ – VIT–)
V
3 V
0.4
1.0
For pullup: VIN = VSS
RPull
Pullup/pulldown resistor
20
35
50
k
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
5
pF
Schmitt-Trigger Inputs
– General Purpose I/O (P1.6 and P1.7, P2.0 to P2.7, and P3.0 and P3.1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
MIN
TYP
MAX
UNIT
1.8 V
0.80
1.40
VIT+
Positive-going input threshold voltage
3 V
1.20
2.00
V
5 V
2.10
2.50
1.8 V
0.45
0.90
VIT–
Negative-going input threshold voltage
3 V
0.75
1.30
V
5 V
1.10
1.60
1.8 V
0.27
0.45
Vhys
Input voltage hysteresis (VIT+ – VIT–)
3 V
0.45
0.65
V
5 V
0.9
1.2
For pullup: VIN = VSS
RPull
Pullup/pulldown resistor
20
35
50
k
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
5
pF
Inputs
– Ports P1 and P2
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC or VIO
MIN
MAX
UNIT
Port P1.0 to P1.5, External trigger pulse width to set
1.8 V to 3.6 V
20
interrupt flag
t(int)
External interrupt timing(2)
ns
Port P1.6 and P1.7, and P2.0 to P2.7, External
1.8 V to 5 V
25
trigger pulse width to set interrupt flag
(1)
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2)
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int).
Leakage Current
– General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Port P1.0 to P1.5, P3.0 to
1.8 V to 3.6 V
±1
±50
P3.7, PJ.0 to PJ.6
High-impedance
Ilkg(Px.y)
(1) (2)
nA
leakage current
Port P1.6 and P1.7, P2.0 to
1.8 V to 5 V
±1
±50
P2.7
(1)
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2)
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
36
Copyright
2010–2011, Texas Instruments Incorporated
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