參數(shù)資料
型號(hào)： MSP430F5132IRSBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, RISC MICROCONTROLLER, PQCC40
封裝： GREEN, PLASTIC, WQFN-40
文件頁數(shù)： 35/102頁
文件大?。?/td> 1183K
代理商： MSP430F5132IRSBT
MSP430F51x1
MSP430F51x2
SLAS619A
– AUGUST 2010 – REVISED AUGUST 2011
Outputs
– Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VIO
MIN
MAX
UNIT
I(OH5max) = –1 mA
(2)
VIO – 0.25
VCC
1.8 V
I(OH5max) = –3 mA
(3)
VIO – 0.60
VCC
I(OH5max) = –2 mA
(2)
VIO – 0.25
VCC
VOH5
High-level output voltage
3 V
V
I(OH5max) = –6 mA
(3)
VIO – 0.60
VCC
I(OH5max) = –4 mA
(2)
VIO – 0.25
VIO
5.0 V
I(OL5max) = -12 mA
(3)
VIO – 0.60
VIO
I(OL5max) = 1 mA
(2)
VSS VSS + 0.25
1.8 V
I(OL5max) = 3 mA
(3)
VSS VSS + 0.60
I(OL5max) = 2 mA
(2)
VSS VSS + 0.25
VOL5
Low-level output voltage
3 V
V
I(OL5max) = 6 mA
(3)
VSS VSS + 0.60
I(OH5max) = 4 mA
(2)
VSS VSS + 0.25
5.0 V
I(OL5max) = 12 mA
(3)
VSS VSS + 0.60
(1)
Selecting reduced drive strength may reduce EMI.
(2)
The maximum total current, I(OH5max) and I(OL5max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(3)
The maximum total current, I(OH5max) and I(OL5max), for all outputs combined, should not exceed ±200 mA to hold the maximum voltage
drop specified.
Output Frequency
– Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VCC = 1.8 V
16
PMMCOREVx = 0
Port output frequency
PJ.0/SMCLK
fPx.y
MHz
(with load)
CL = 20 pF, RL = 1 k
(1) (2)
VCC = 3 V
25
PMMCOREVx = 3
VCC = 1.8 V
PJ.3/ACLK
16
PMMCOREVx = 0
PJ.0/SMCLK
fPort_CLK
Clock output frequency
MHz
PJ.1/MCLK
VCC = 3 V
25
CL = 20 pF
(2)
PMMCOREVx = 3
(1)
A resistive divider with 2
× 0.5 k between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2)
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Output Frequency
– Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VCC = 1.8 V, VIO = 1.8 V
16
PMMCOREVx = 0
Port output frequency
P1.6 port mapper SMCLK from P3.4
VCC = 3 V, VIO = 3 V
fPx.y
25
MHz
(with load)
CL = 20 pF, RL = 1 k
(1) (2)
PMMCOREVx = 3
VCC = 3 V, VIO = 5 V
25
PMMCOREVx = 3
VCC = 1.8 V, VIO = 1.8V
16
PMMCOREVx = 0
P1.6 port mapper SMCLK from P3.4
VCC = 3 V, VIO = 3 V
fPort_CLK
Clock output frequency
25
MHz
CL = 20 pF
(2)
PMMCOREVx = 3
VCC = 3 V, VIO = 5 V
25
PMMCOREVx = 3
(1)
A resistive divider with 2
× 0.5 k between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2)
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
38
Copyright
2010–2011, Texas Instruments Incorporated
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