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| 型號： | MSP430F5508IPT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC48 |
| 封裝： | PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 55/99頁 |
| 文件大小： | 1134K |
| 代理商： | MSP430F5508IPT |
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PRODUCTPREVIEW
MSP430F550x
www.ti.com
SLAS645B – JULY 2009 – REVISED JULY 2010
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SVMLE = 0, PMMCOREV = 2
0
nA
I(SVML)
SVML current consumption
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
2.0
A
SVMLE = 1, dVCORE/dt = 10 mV/s, SVMLFP = 1
2.5
tpd(SVML)
SVML propagation delay
s
SVMLE = 1, dVCORE/dt = 1 mV/s, SVMLFP = 0
20
SVMLE = 0
→ 1, SVMLFP = 1
12.5
t(SVML)
SVML on/off delay time
s
SVMLE = 0
→ 1, SVMLFP = 0
100
Wake-Up From Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
PMMCOREV = SVSMLRRL = n,
fMCLK ≥ 4.0 MHz
5
tWAKE-UP-
Wake-up time from LPM2, LPM3, or
where n = 0, 1, 2, or 3
s
FAST
LPM4 to active mode(1)
fMCLK < 4.0 MHz
6
SVSLFP = 1
tWAKE-UP-
Wake-up time from LPM2, LPM3 or
PMMCOREV = SVSMLRRL = n, where n = 0, 1, 2, or 3
150
165
s
SLOW
LPM4 to active mode(2)
SVSLFP = 0
tWAKE-UP-
Wake-up time from LPM4.5 to active
2
3
ms
LPM5
mode(3)
tWAKE-UP-
Wake-up time from RST or BOR event to
2
3
ms
RESET
active mode(3)
(1)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
Family User's Guide (SLAU208).
(2)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide
(SLAU208).
(3)
This value represents the time from the wakeup event to the reset vector execution.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
1.8 V/
fTA
Timer_A input clock frequency
External: TACLK
25
MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs.
1.8 V/
tTA,cap
Timer_A capture timing
Minimum pulse width required for
20
ns
3.0 V
capture.
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
1.8 V/
fTB
Timer_B input clock frequency
External: TBCLK
25
MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs.
1.8 V/
tTB,cap
Timer_B capture timing
Minimum pulse width required for
20
ns
3.0 V
capture.
Copyright 2009–2010, Texas Instruments Incorporated
59
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