參數(shù)資料
型號: MSP430F5513IRGC
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC64
封裝: GREEN ,PLASTIC, VQFN-64
文件頁數(shù): 90/115頁
文件大小: 1159K
代理商: MSP430F5513IRGC
MSP430F551x
MSP430F552x
SLAS590D – OCTOBER 2009 – REVISED APRIL 2010
www.ti.com
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
2
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
2
mA
tCPT
Cumulative program time
See (1)
16
ms
Program/erase endurance
104
105
cycles
tRetention
Data retention duration
TJ = 25°C
100
years
tWord
Word or byte program time
See (2)
64
85
s
tBlock, 0
Block program time for first byte or word
See (2)
49
65
s
Block program time for each additional byte or word, except for last
tBlock, 1–(N–1)
See (2)
37
49
s
byte or word
tBlock, N
Block program time for last byte or word
See (2)
55
73
s
Erase time for segment, mass erase, and bank erase when
tErase
See (2)
23
32
ms
available.
MCLK frequency in marginal read mode
fMCLK,MGR
0
1
MHz
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1)
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2)
These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
s
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
tSBW, En
2.2 V/3 V
1
s
edge)(1)
tSBW,Rst
Spy-Bi-Wire return to normal operation time
15
100
s
2.2 V
0
5
MHz
fTCK
TCK input frequency - 4-wire JTAG(2)
3 V
0
10
MHz
Rinternal
Internal pulldown resistance on TEST
2.2 V/3 V
45
60
80
k
(1)
Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2)
fTCK may be restricted to meet the timing requirements of the module selected.
76
Copyright 2009–2010, Texas Instruments Incorporated
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