Preliminary
2003 Fairchild Semiconductor Corporation
DS500782
www.fairchildsemi.com
May 2002
Revised February 2003
MSX340
340
Port
Di
git
a
lCrosspo
int
Swit
ch
w
ith
L
V
TTL
I/
O
’s
(P
rel
imin
a
ry)
MSX340
340 Port Digital Crosspoint Switch with LVTTL I/O’s
(Preliminary)
General Description
The MSX
family of SRAM-based bit-oriented switching
devices offer flow-through NRZ data rates of up to 150Mb/s
and registered clock frequencies of up to 75MHz. The I/O
Buffers are individually configurable. The I/O buffers can be
connected to each other through the switch matrix, which
supports One-to-One and One-to-Many connections.
The proprietary RapidConfigure
parallel interface allows
fast configuration of both the I/O buffers and switch matrix.
It also allows readback of the device for test and verifica-
tion purposes. The MSX devices also support the industry
standard JTAG (IEEE 1149.1) interface for boundary scan
testing. The JTAG interface can also be used to download
configuration data to the device. A functional block diagram
of the MSX architecture is shown in Figure 1.
Features
s SRAM-based, in-system programmable
s Configurable I/O Ports
Individually programmable as input, output,
bi-directional, or Bus Repeater
mode
Control Signals per I/O port: 2 input enables, 2 output
enables, 2 Global Clock inputs and Next Neighbor
Clock option
Output data inversion: capable of inverting output
signals in flow through mode
s Non-blocking switch matrix
One-to-One and One-to-Many connections
Double-buffered
configuration
RAM
cells
for
simultaneous global updates
s Registered and flow-through data modes
Up to 75 MHz clock frequency in registered mode
Up to 150 Mb/s in flow-through mode
s 20 ns propagation delay in flow-through mode
s 8 mA output current
s Dedicated RapidConfigure parallel interface or JTAG
serial interface available for configuration and readback
of MSX devices
s 3.3V operation, LVTTL I/O’s (5V tolerant)
s MSX340 is offered in a 480 PBGA package
Applications
Telecom and datacom switching
Video switches and servers
Test equipment
Ordering Code:
MSX
, Bus Repeater, and RapidConfigure are trademarks of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
MSX340PB480
BGA480A
480-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.27mm Pitch,
37.5mm Square