參數(shù)資料
型號(hào): MSP430F5632IZQWR
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PBGA113
封裝: GREEN, PLASTIC, BGA-113
文件頁(yè)數(shù): 30/101頁(yè)
文件大?。?/td> 1073K
代理商: MSP430F5632IZQWR
PRODUCTPREVIEW
MSP430F563x
SLAS650A – JUNE 2010 – REVISED JULY 2010
www.ti.com
Table 39. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
Table 40. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA General Control: DMA module control 0
DMACTL0
00h
DMA General Control: DMA module control 1
DMACTL1
02h
DMA General Control: DMA module control 2
DMACTL2
04h
DMA General Control: DMA module control 3
DMACTL3
06h
DMA General Control: DMA module control 4
DMACTL4
08h
DMA General Control: DMA interrupt vector
DMAIV
0Ah
DMA Channel 0 control
DMA0CTL
00h
DMA Channel 0 source address low
DMA0SAL
02h
DMA Channel 0 source address high
DMA0SAH
04h
DMA Channel 0 destination address low
DMA0DAL
06h
DMA Channel 0 destination address high
DMA0DAH
08h
DMA Channel 0 transfer size
DMA0SZ
0Ah
DMA Channel 1 control
DMA1CTL
00h
DMA Channel 1 source address low
DMA1SAL
02h
DMA Channel 1 source address high
DMA1SAH
04h
DMA Channel 1 destination address low
DMA1DAL
06h
DMA Channel 1 destination address high
DMA1DAH
08h
DMA Channel 1 transfer size
DMA1SZ
0Ah
DMA Channel 2 control
DMA2CTL
00h
DMA Channel 2 source address low
DMA2SAL
02h
DMA Channel 2 source address high
DMA2SAH
04h
DMA Channel 2 destination address low
DMA2DAL
06h
DMA Channel 2 destination address high
DMA2DAH
08h
DMA Channel 2 transfer size
DMA2SZ
0Ah
DMA Channel 3 control
DMA3CTL
00h
DMA Channel 3 source address low
DMA3SAL
02h
DMA Channel 3 source address high
DMA3SAH
04h
DMA Channel 3 destination address low
DMA3DAL
06h
DMA Channel 3 destination address high
DMA3DAH
08h
DMA Channel 3 transfer size
DMA3SZ
0Ah
DMA Channel 4 control
DMA4CTL
00h
DMA Channel 4 source address low
DMA4SAL
02h
34
Copyright 2010, Texas Instruments Incorporated
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