參數(shù)資料
型號： MSP430F5632IZQWR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PBGA113
封裝： GREEN, PLASTIC, BGA-113
文件頁數(shù)： 41/101頁
文件大?。?/td> 1073K
代理商： MSP430F5632IZQWR
PRODUCTPREVIEW
MSP430F563x
SLAS650A – JUNE 2010 – REVISED JULY 2010
www.ti.com
Outputs – General Purpose I/O (Full Drive Strength) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
I(OLmax) = 3 mA
(1)
VSS VSS + 0.25
1.8 V
I(OLmax) = 10 mA
(2)
VSS VSS + 0.60
VOL
Low-level output voltage
V
I(OLmax) = 5 mA
(1)
VSS VSS + 0.25
3 V
I(OLmax) = 15 mA
(2)
VSS VSS + 0.60
Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
I(OHmax) = –1 mA
(2)
VCC – 0.25
VCC
1.8 V
I(OHmax) = –3 mA
(3)
VCC – 0.60
VCC
VOH
High-level output voltage
V
I(OHmax) = –2 mA
(2)
VCC – 0.25
VCC
3 V
I(OHmax) = –6 mA
(3)
VCC – 0.60
VCC
I(OLmax) = 1 mA
(2)
VSS VSS + 0.25
1.8 V
I(OLmax) = 3 mA
(3)
VSS VSS + 0.60
VOL
Low-level output voltage
V
I(OLmax) = 2 mA
(2)
VSS VSS + 0.25
3 V
I(OLmax) = 6 mA
(3)
VSS VSS + 0.60
(1)
Selecting reduced drive strength may reduce EMI.
(2)
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3)
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – Ports P1, P2 and P3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VCC = 1.8 V
8
PMMCOREVx = 0
Port output frequency
P3.4/TA2CLK/SMCLK/S27
fPx.y
MHz
(with load)
CL = 20 pF, RL = 1 k
(1) or 3.2 k(2) (3)
VCC = 3 V
20
PMMCOREVx = 3
VCC = 1.8 V
P1.0/TA0CLK/ACLK/S39
8
PMMCOREVx = 0
P3.4/TA2CLK/SMCLK/S27
fPort_CLK
Clock output frequency
MHz
P2.0/P2MAP0 (P2MAP0 = PM_MCLK )
VCC = 3 V
20
CL = 20 pF
(3)
PMMCOREVx = 3
(1)
Full drive strength of port: A resistive divider with 2 × 0.5 k
between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
(2)
Reduced drive strength of port: A resistive divider with 2 × 1.6 k
between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
(3)
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
44
Copyright 2010, Texas Instruments Incorporated
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