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參數(shù)資料
| 型號(hào)： | MT16VR12816AG-845B1 |
| 元件分類： | DRAM |
| 英文描述： | 128M X 16 RAMBUS MODULE, 45 ns, DMA84 |
| 封裝： | RIMM-184 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 183K |
| 代理商： | MT16VR12816AG-845B1 |
4
32, 48, 64, 128 Meg x 16/18 Rambus RIMM Modules
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RM01.p65 – Rev. 9/99
1999, Micron Technology, Inc.
32, 48, 64, 128 MEG x 16/18
RAMBUS RIMM MODULES
ADVANCE
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
I/O
TYPE
DESCRIPTION
102
LCFM
I
RSL
Clock from Master: Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
104
LCFMN
I
RSL
Clock from Master: Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
12
LCTMN
I
RSL
Clock to Master: Interface clock used for transmitting
RSL signals from the Channel. Negative polarity.
14
LCTM
I
RSL
Clock to Master: Interface clock used for transmitting
RSL signals from the Channel. Positive polarity.
2, 94, 4, 96, 6, 98, 8,
LDQA8..0
I/O
RSL
Data Bus A: A 9-bit bus carrying a byte of read or write
100, 10
data between the Channel and the RDRAM. LDQA8 is
non-functional on x16 devices.
124, 32, 122, 30, 120,
LDQB8..0
I/O
RSL
Data Bus B: A 9-bit bus carrying a byte of read or write
28, 118, 26, 116
data between the Channel and the RDRAM. LDQB8 is
non-functional on x16 devices.
108, 18, 110
LROW2..0
I
RSL
Row Bus: 3-bit bus containing control and address
information for row accesses.
20, 112, 22, 114, 24
LCOL4..0
I
RSL
Column Bus: 5-bit bus containing control and address
information for Column accesses.
175
RCFM
I
RSL
Clock from Master: Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
173
RCFMN
I
RSL
Clock from Master: Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
81
RCTMN
I
RSL
Clock to Master: Interface clock used for transmitting
RSL signals from the Channel. Negative polarity.
79
RCTM
I
RSL
Clock to Master: Interface clock used for transmitting
RSL signals from the Channel. Positive polarity.
91, 183, 89, 181, 87,
RDQA8..0
I/O
RSL
Data Bus A: A 9-bit bus carrying a byte of read or write
179, 85, 177, 83
data between the Channel and the RDRAM. RDQA8 is
non-functional on x16 devices.
153, 61, 155, 63, 157,
RDQB8..0
I/O
RSL
Data Bus B: A 9-bit bus carrying a byte of read or write
65, 159, 67, 161
data between the Channel and the RDRAM. RDQB8 is
non-functional on x16 devices.
169, 75, 167
RROW2..0
I
RSL
Row Bus: 3-bit bus containing control and address
information for row accesses.
73, 165, 71, 163, 69
RCOL4..0
I
RSL
Column Bus: 5-bit bus containing control and address
information for Column accesses.
36
SOUT
I/O
CMOS
Serial I/O: Pin for reading from and writing to the control
registers. Attaches to SIO1 of the last RDRAM on the
module.
128
SIN
I/O
CMOS
Serial I/O: Pin for reading from and writing to the control
registers. Attaches to SIO0 of the first RDRAM on the
module.
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