參數(shù)資料
型號(hào): MT18VDDT12872PHIG-265XX
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200
封裝: SODIMM-200
文件頁(yè)數(shù): 1/39頁(yè)
文件大?。?/td> 816K
代理商: MT18VDDT12872PHIG-265XX
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
09005aef808ffdc7
DD9_18C16_32_64_128X72PHG_E.fm - Rev. E 7/03 EN
1
2003 Micron Technology, Inc. All rights reserved.
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
DDR SDRAM
SMALL-OUTLINE DIMM
MT9VDDT1672PH(I) – 128MB, MT9VDDT3272PH(I) –
256MB, MT18VDDT6472PH(I) – 512MB,
MT9VDDT6472PH(I) – 512MB,
MT18VDDT12872PH(I) – 1GB
For the lastest data sheet, please refer to the Micron
Features
200-pin, small-outline, dual in-line memory
module (SODIMM)
ECC, 1-bit error detection and correction
Fast data transfer rates: PC1600, PC2100, and
PC2700
Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
MT9VDDT1672PH (16 Meg x 72); MT9VDDT3272PH (32 Meg
x 72); MT18VDDT6472PH (64 Meg x 72); MT9VDDT6472PH
(32 Meg x 72, stacked); MT18VDDT12872PH (64 Meg x 72,
stacked)
VDD = VDDQ = +2.5V
VDDSPD = +2.3V to +3.6V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
NOTE:
1. CL = Device CAS (READ) Latency.
2. -335 and -262 speed grades available in single-
rank module only.
3. Consult Micron for availability; industrial tem-
perature option available in -265 speed only.
Figure 1: 200-Pin SODIMM (MO-224)
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
Four internal device banks for concurrent operation
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
15.625s (MT9VDDT1672PH), 7.8125s
(MT9VDDT3272PH, MT18VDDT6472PH,
MT9VDDT6472PH, MT18VDDT12872PH)
maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Programmable READ CAS latency
Gold edge contacts
Bidirectional data strobe (DQS) transmitted/re-
ceived with data—i.e., source-synchronous data
capture
Differential clock inputs CK and CK#
OPTIONS
MARKING
Operating Temperature Range
Commercial (0°C
TA +70°C)
None
Industrial (-40°C
TA +85°C)
I3
Package
200-pin SODIMM (standard)
G
200-pin SODIMM (lead-free)
Y
Clock Frequency/CAS Latency
6ns, 267 MHz (333 MT/s) / CL = 2.51
7.5ns, 133 MHz (266 MT/s)/ CL = 2
-262
7.5ns, 133 MHz (266 MT/s)/ CL = 2
-26A
7.5ns, 133 MHz (266 MT/s)/ CL = 2.5
-265
10ns, 100 MHz (200 MT/s)/ CL = 2
-202
PCB
Standard: 1.5in. (38.10mm)
Low-Profile: 1.25in. (31.75mm)
Standard: 1.50in. (38.10mm)
Low Profile: 1.25in. (31.75mm)
Table 1:
Address Table
MT9VDDT1672PH MT9VDDT3272PH
MT18VDDT6472PH MT9VDDT6472PH MT18VDDT12872PH
Refresh Count
4K
8K
Row Addressing
4K (A0–A11)
8K (A0–A12)
DeviceBankAddressing
4 (BA0, BA1)
Base Device Configuration
16 Meg x 8
32 Meg x 8
64 Meg x 8
Column Addressing
1K (A0–A9)
2K (A0–A9, A11)
Module Rank Addressing
1 (S0#)
2 (S0#, S1#)
1 (S0#)
2 (S0#, S1#)
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