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參數(shù)資料
| 型號： | MT28C256564W18SBT-F705P70BTWT |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | LEAD FREE, FBGA-88 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大小： | 218K |
| 代理商： | MT28C256564W18SBT-F705P70BTWT |
256Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
PRELIMINARY
09005aef80bcd58d
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C256564W18S.fm - Rev. D Pub 2/04 EN
5
2004 Micron Technology. Inc. All rights reserved.
Device General Description
The MT28C256532W18S/MT28C256564W18S com-
bination Flash and CellularRAM is a high-performance,
high-density, memory solution that can significantly
improve system performance. This memory solution is
comprised of two 128Mb Flash devices and one 32Mb
or one 64Mb CellularRAM device.
It is important to note that the specifications con-
tained in this document supersede the specifications
listed in the referenced individual Flash and Cellular-
RAM data sheets.
For all asynchronous/page Flash devices, the Burst
mode specifications in the referenced Flash discrete
data sheet should be ignored, as they do not pertain to
asynchronous/page mode operation.
Flash General Description
The Flash architecture features a multipartition
configuration that supports READ-while-PROGRAM/
ERASE operations with no latency. An 8Mb partition
size enables optimal design flexibility.
Two Flash devices are stacked to achieve the 256Mb
density. Both Flash die share a dedicated CE# and OE#
control.
The stacked Flash device enables soft protection for
blocks, as read only, by configuring soft protection reg-
isters with dedicated command sequences. For secu-
rity purposes, two user-programmable 64-bit chip
protection registers are provided for each Flash device.
The embedded WORD PROGRAM and BLOCK
ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.
Each Flash device has a read configuration register
(RCR) that defines how the Flash interacts with the
memory bus. For device specifications and additional
documentation concerning Flash, please refer to the
MT28F1284W18 data sheet at www.micron.com/flash.
Flash Configurations
Each Flash memory implements a multibank archi-
tecture (16 banks of 8Mb each) to allow concurrent
operations. Any address within a block address range
selects that block for the required READ, PROGRAM, or
ERASE operation.
Each Flash memory features eight 8K-word sectors
(8 x 65,536 bits), designated as parameter blocks, and
the remaining part is organized in main blocks of 64K
words each (524,288 bits). The parameter blocks are
addressed either by the low order addresses (bottom
boot) or by the higher order addresses (top boot).
The two Flash devices can be supplied with any
combination of top or bottom boot (e.g., top/top, bot-
tom/bottom, top/bottom, or bottom/top). Please see
CellularRAM General Description
The CellularRAM architecture features high-speed
CMOS, dynamic random-access memories developed for
low-power portable applications The CellularRAM device
is available in either 32Mb or 64Mb densities.
To operate seamlessly on a burst Flash bus,
CellularRAM products have incorporated a transparent
self-refresh mechanism. The hidden refresh requires no
additional support from the system memory controller
and has no significant impact on device read/write
performance.
The configuration register (CR) is used to control how
refresh is performed on the CellularRAM array. These
registers are automatically loaded with default settings
during power-up and can be updated any time during
normal operation. Special attention has been focused
on standby current consumption during self-refresh.
CellularRAM products include three system-acces-
sible mechanisms used to minimize standby current.
Partial array refresh (PAR) limits refresh to the portion
of the memory array being used. Temperature com-
pensated refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased at lower temperatures to
minimize current consumption during standby. Deep
sleep mode halts the refresh operation altogether and
is used when no vital information is stored in the
device. These three refresh mechanisms are adjusted
through the configuration register (CR).
For
device
specifications
and
additional
documentation concerning CellularRAM memory, please
refer
to
the
MT45W2MW16PFA
and
MT45W4MW16PFA
CellularRAM
data
sheets
at
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