參數(shù)資料
型號(hào)： MT28C64464W18ABW-F605P70TWT
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA77
封裝： 8 X 10 MM, LEAD FREE, FBGA-77
文件頁(yè)數(shù)： 13/13頁(yè)
文件大小： 239K
代理商： MT28C64464W18ABW-F605P70TWT
64Mb MULTIBANK ASYNC/PAGE OR BURST FLASH
16Mb/32Mb/64Mb ASYNC/PAGE CellularRAM
09005aef80c9c807
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C64432W18A.fm - Rev. F Pub 2/04 EN
9
2003 Micron Technology. Inc. All rights reserved.
MultiChip Packaging Considerations
Multichip packaging presents unique chal-
lenges when controlling complex memory devices.
The MT28C64416W18/W30A, MT28C64432W18/
W30A, and MT28C644644W18/W30A devices com-
bine one Micron Flash device with a single Cellular-
RAM device.
Unique IDs, State Machines, and
Registers
The Flash device has a command state machine
(CSM) and status register (SR) and read configuration
register (RCR). The Flash device has its own OTP, CFI,
and device code. Depending on the boot configura-
tion of the device, the OTP, CFI, and device code infor-
mation may differ.
The CellularRAM device has a configuration register
(CR) that defines how the device performs self refresh.
WAIT Ball Operation
The WAIT ball polarity for the Flash device is config-
ured by programming bit 10 in the read configuration
register (RCR). The default setting for the WAIT ball is
active LOW.
Power Consumption
Multiple chip packaging requires that power
calculations consider the active operation of the
Flash as well as that of the CellularRAM.
Total
power consumed will be the sum of the currents
associated with the state of each device.
NOTE:
1. WAIT status is only valid for burst mode operation. WAIT should be ignored for all other operating modes.
2. Not used in asynchronous/page non-latched operation. For latched operation, please refer to the Flash discrete data
sheet.
3. Not used in asynchronous/page operation.
Table 2:
Truth Table
MODES
FLASH SIGNALS
CellularRAM SIGNALS
MEMORY
OUTPUT
F_CE# F_OE# F_WE# F_RST# F_ADV#2 F_WAIT#3 C_CE#
C_ZZ#
C_OE#
C_UB/LB#
C_WE#
MEMORY
BUS
CONTROL
DQ0–
DQ15
FLAS
H
Read
LL
H
L
Active1
CellularRAM memory must be in High-Z
Flash
DOUT
Write
L
H
L
H
X
Asserted
Flash
DIN
Standby
HX
X
H
X
High-Z
CellularRAM memory any mode
allowable
Other
High-
Z
Output
Disable
LH
H
X
Active1
Other
High-
Z
Reset
X
L
X
High-Z
None
High-
Z
C
e
ll
ul
arRA
M
MEMORY
Read
Flash must be in High-Z
LHL
L
H
Cellular
RAM
DOUT
Write
LH
H
L
Cellular
RAM
DIN
Standby
Flash any mode allowable
HH
X
Other
High-
Z
Output
Disable
LH
H
X
H
Other
High-
Z
Deep
Sleep
Mode
HL
X
Other
High-
Z
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