- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224505 > MT41J512M4JE-187EIT:A 64M X 4 DDR DRAM, PBGA82 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT41J512M4JE-187EIT:A |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, PBGA82 |
| 封裝： | 12.50 X 15 MM, LEAD FREE, FBGA-82 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大小： | 288K |
PDF: 09005aef826aaadc/Source: 09005aef826a65af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2Gb DDR3 SDRAM.fm - Rev. C 12/07 EN
3
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8 DDR3 SDRAM
General Description
Advance
General Description
The 2Gb DDR3 SDRAM is a high-speed CMOS, dynamic random-access memory
containing 2,147,483,648 bits. It is internally configured as an 8-bank DRAM.
The 2Gb DDR3 SDRAM uses a double data rate architecture to achieve high-speed oper-
ation. The double data rate architecture is essentially an 8n-prefetch architecture with
an interface designed to transfer two data words per clock cycle at the I/O balls. A single
read or write access for the 2Gb DDR3 SDRAM effectively consists of a single 8n-bit wide,
one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O balls.
The differential data strobe (DQS/DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM edge-aligned to the data
strobes.
The 2Gb DDR3 SDRAM operates from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on first rising edge of DQS after the one cycle WRITE preamble,
and output data is referenced on the first rising edge of DQS after the one cycle READ
preamble.
Read and write accesses to the DDR3 SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR3 SDRAM uses read and write burst lengths of eight. An auto precharge func-
tion may be enabled to provide a self-timed row precharge that is initiated at the end of
the burst access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high effective bandwidth by hiding
row precharge and activation time. A self refresh mode is provided, along with a power-
saving power-down mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT42C8255RG-7TR | 256K X 8 VIDEO DRAM, 70 ns, PDSO40 |
| MT46V32M16TG-75ELIT | 32M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V32M16BN-5BLIT | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| MT46V32M81AZ4-6T:G | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT41J512M4V79D3WC1 | 制造商:Micron Technology Inc 功能描述:512MX4 DDR3 SDRAM DIE-COM COMMERCIAL 1.5V - Trays |
| MT41J512M4V89C3WC1 | 制造商:Micron Technology Inc 功能描述:512MX4 DDR3 SDRAM DIE-COM COMMERCIAL 1.5V - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。