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| 型號： | MT46V32M8BG-6AT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封裝： | (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 77/93頁 |
| 文件大?。?/td> | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
77
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 42:
WRITE-to-READ – Uninterrupting
Notes:
1. DI b = data-in for column b; DO n = data-out for column n.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case tWTR is not required, and the READ
command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
tDQSS (NOM)
CK
CK#
Command
WRITE
NOP
READ
NOP
Address
Bank a,
Col b
Bank a,
Col n
NOP
T0
T1
T2
T3
T2n
T4
T5
T1n
T6
T6n
tWTR
CL = 2
DQ
DQS
DM
DI
b
DO
n
tDQSS
tDQSS (MIN)
CL = 2
DQ
DQS
DM
DI
b
DO
n
tDQSS
tDQSS (MAX)
CL = 2
DQ
DQS
DM
DI
b
DO
n
tDQSS
Don’t Care
Transitioning Data
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