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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN

256Mb: x4, x8, x16 DDR SDRAM

Operations

Power-down (CKE Not Active)

Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in

progress, from the issuing of a READ or WRITE command, until completion of the

access. Thus a clock suspend is not supported. For READs, an access completion is

defined when the read postamble is satisfied; for WRITEs, when the write recovery time

(tWR) is satisfied.

Power-down, as shown in Figure 55 on page 91, is entered when CKE is registered LOW

and all criteria in Table 33 on page 47 are met. If power-down occurs when all banks are

idle, this mode is referred to as precharge power-down; if power-down occurs when a

row is active in any bank, this mode is referred to as active power-down. Entering power-

down deactivates the input and output buffers, excluding CK, CK#, and CKE. For

maximum power savings, the DLL is frozen during precharge power-down mode. Exiting

power-down requires the device to be at the same voltage and frequency as when it

entered power-down. However, power-down duration is limited by the refresh require-

ments of the device (tREFC or tREFCAT).

While in power-down, CKE LOW and a stable clock signal must be maintained at the

inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-

down state is synchronously exited when CKE is registered HIGH (in conjunction with a

NOP or DESELECT command). A valid executable command may be applied one clock

cycle later.

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