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參數(shù)資料
| 型號： | MT48H8M16LFB4-8IT:JTR |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件頁數(shù)： | 7/61頁 |
| 文件大?。?/td> | 2469K |
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PDF: 09005aef8237e877/Source: 09005aef8237e8d8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. A 6/06 EN
15
2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Commands
Preliminary
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a
written description of each command. Three additional Truth Tables appear following
"Operation" on page 18; these tables provide current state/next state information.
Notes:
1. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
2. A0-A11 define op-code written to mode register.
3. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0–A8 provide column address; A10 HIGH enables the auto precharge feature (non persis-
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank
is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay). DQML controls DQ0–7, DQMH controls DQ8–15.
9. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when CKE
is LOW.
10. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
could coincide with data on the bus. However the DQs column reads a “Don’t Care” state to
illustrate that the BURST TERMINATE command can occur when there is no data present.
Table 6:
Truth Table 1 – Commands and DQM Operation
Note 1
Name (Function)
CS#
RAS
#
CAS
#
WE#
DQM
ADDR
DQs
Notes
COMMAND INHIBIT (NOP)
H
XXX
X
NO OPERATION (NOP)
L
HHH
X
ACTIVE (Select bank and activate row)
LL
H
X
Bank/Row
X
READ (Select bank and column, and start READ burst)
LH
L/H
Bank/Col
X
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L/H
Bank/Col
Valid
BURST TERMINATE or DEEP POWER-DOWN
(Enter deep power-down mode)
LH
H
L
X
PRECHARGE (Deactivate row in bank or banks)
L
H
L
X
Bank, A10
X
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LLL
H
X
LOAD MODE REGISTER/LOAD EXTENDED MODE
REGISTER
LLLL
X
Op-Code
X
Write Enable/Output Enable
XXXX
L
X
Active
Write Inhibit/Output High-Z
XXXX
H
X
High-Z
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT48H8M16LFF3-7E | 制造商:Micron Technology Inc 功能描述: |
| MT48H8M16LFF4-10 | 功能描述:IC SDRAM 128MBIT 100MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT48H8M16LFF4-10 IT | 功能描述:IC SDRAM 128MBIT 100MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT48H8M16LFF4-8 | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT48H8M16LFF4-8 IT | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
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