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參數(shù)資料
| 型號： | MT48LC1M16A1S |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 12/51頁 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
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16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
12
16Mb: x16
SDRAM
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be
issued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 3).
After opening a row (issuing an ACTIVE com-
mand) a READ or WRITE command may be issued to
that row, subject to the
t
RCD specification.
t
RCD
(MIN) should be divided by the clock period and
rounded up to the next whole number to determine
the earliest clock edge after the ACTIVE command on
which a READ or WRITE command can be issued. For
example, a
t
RCD specification of 20ns with a 125 MHz
clock (8ns period) results in 2.5 clocks rounded to 3.
This is reflected in Figure 4, which covers any case where
2 <
t
RCD (MIN)/
t
CK
≤
3. (The same procedure is used
to convert other specification limits from time units to
clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
t
RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
RRD.
CS#
WE#
CAS#
RAS#
CKE
CLK
A0-A10
BA
ROW
ADDRESS
HIGH
BANK 0
BANK 1
Figure 3
Activating a Specific Row in a
Specific Bank
Figure 4
Example: Meeting
t
RCD (MIN) When 2 <
t
RCD (MIN)/
t
CK
≤
3
CLK
T2
T1
T3
T0
t
COMMAND
NOP
ACTIVE
READ or
WRITE
T4
NOP
RCD
DON
’
T CARE
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
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| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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