參數(shù)資料
型號： MT48LC1M16A1S
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁數(shù)： 37/51頁
文件大?。?/td> 1480K
代理商： MT48LC1M16A1S
16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
37
16Mb: x16
SDRAM
AUTO REFRESH MODE
tCH
tCL
tCK
CKE
CLK
DQ
tRCAR
()()
(
)(
)(
)
(
)
tRP
()()
(
)(
)(
)
(
)
(
)(
)(
)
(
)
()()
COMMAND
tCMH
tCMS
NOP
NOP
(
)(
)(
)
(
)
BANK,
ROW
ACTIVE
AUTO
REFRESH
(
)(
)(
)
(
)
NOP
NOP
PRECHARGE
Precharge all
active banks.
AUTO
REFRESH
tRC
High-Z
ADDRESS
BANK(S)
(
)(
)(
)
(
)
tAH
tAS
tCKH
tCKS
()()
NOP
DQM
1
(
)(
)(
)
(
)
(
)(
)(
)
(
)
DON
’
T CARE
UNDEFINED
T0
T1
T2
Tn + 1
To + 1
-6
-7
-8A
SYMBOL*
t
CKH
t
CKS
t
CMH
t
CMS
t
RC
t
RCAR
t
RP
MIN
1
2
1
2
60
66
18
MAX
MIN
1
2
1
2
70
70
21
MAX
MIN
1
2
1
2
80
80
24
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CK (1)
MIN
1
2
2.5
2.5
6
8
20
MAX
MIN
1
2
2.75
2.75
7
10
25
MAX
MIN
1
2
3
3
8
13
25
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE:
1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
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