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參數(shù)資料
| 型號(hào)： | MT48LC1M16A1S |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 33/51頁 |
| 文件大?。?/td> | 1480K |
| 代理商： | MT48LC1M16A1S |
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16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
33
16Mb: x16
SDRAM
12. Other input signals are allowed to transition no more
than once in any two-clock period and are otherwise at
valid V
IH
or V
IL
levels.
13. I
DD
specifications are tested after the device is properly
initialized.
14. Timing actually specified by
t
CKS; clock(s) specified as a
reference only at minimum cycle rate.
15. Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC functionality and
are not dependent on any timing parameter.
18. The I
DD
current will decrease as the CAS latency is
reduced. This is due to the fact that the maximum cycle
rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two-
clock period.
20. CLK must be toggled a minimum of two times during this
period.
21. Based on
t
CK = 166 MHz for -6, 143 MHz for -7 and 125
MHz for -8A.
22. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 2V for a pulse width
≤
3ns, and the pulse width cannot be greater than one
third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V
for a pulse width
≤
3ns. The pulse width cannot be
greater than one third of the cycle rate.
23. The clock frequency must remain constant during access
or precharge states (READ, WRITE, including
t
WR, and
PRECHARGE commands). CKE may be used to reduce the
data rate.
24. Auto precharge mode only.
25. Precharge mode only.
26.
t
CK = 6ns for -6, 7ns for -7, 8ns for -8A.
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
DD
, V
DD
Q = +3.3V; f = 1
MHz,
t
A = 25
°
C.
3.
I
DD
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle time
and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0
°
C
≤
T
≤
70
°
C) is ensured.
6.
An initial pause of 100μs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (V
DD
and V
DD
Q must
be powered up simultaneously. V
SS
and V
SS
Q must be at
same potential.) The two AUTO REFRESH command wake-
ups should be repeated any time the
t
REF refresh
requirement is exceeded.
7.
AC characteristics assume
t
T = 1ns.
8.
transition rate specification, the clock and CKE must
transit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a
monotonic manner.
9.
Outputs measured at 1.4V with equivalent load:
In addition to meeting the
Q
30pF
10.
t
HZ defines the time at which the output achieves the
open circuit condition; it is not a reference to V
OH
or
V
OL
. The last valid data element will meet
t
OH before
going High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 2.8V with
timing referenced to 1.4V crossover point.
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|---|---|
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| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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