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| 型號： | MT48LC4M32LFB5-10ES:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| 封裝： | 8 X 13 MM, LEAD FREE, VFBGA-90 |
| 文件頁數(shù)： | 6/69頁 |
| 文件大?。?/td> | 6213K |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
14
2001 Micron Technology, Inc. All rights reserved.
NOTE:
1. For full-page accesses: y = 512 (x16), y = 256 (x32).
2. For a burst length of two, A1-A8 (x16) or A1-A7 (x32)
select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-A8 (x16) or A2-A7 (x32)
select the block-of-four burst; A0-A1 select the starting
column within the block.
4. For a burst length of eight, A3-A8 (x16) or A3-A7 (x32)
select the block-of-eight burst; A0-A2 select the start-
ing column within the block.
5. For a full-page burst, the full row is selected and A0-A8
(x16) or A0-A7 (x32) select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A8 (x16) or A0-A7 (x32)
select the unique column to be accessed, and mode
register bit M3 is ignored.
CAS Latency
The CAS latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to one, two, or three clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a read command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
cates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Figure 8: CAS Latency
Table 6:
Burst Definition
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN
A BURST
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
2A0
00-1
0-1
11-0
1-0
4A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page (y)
n = A0-A8 for
x16, A0-A7
for x32
(location 0-y)
Cn, Cn + 1,
Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Not Supported
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T0
CAS Latency = 1
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
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