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| 型號： | MT48LC4M32LFB5-10ES:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| 封裝： | 8 X 13 MM, LEAD FREE, VFBGA-90 |
| 文件頁數(shù)： | 9/69頁 |
| 文件大?。?/td> | 6213K |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
17
2001 Micron Technology, Inc. All rights reserved.
Commands
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
following the Operation section; these tables provide
current state/next state information.
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 define the op-code written to the mode register. BA0-BA1 select either the mode register or the extended mode
register (BA0=BA1=0 select the mode register, BA1=1, BA0=0 selects the extended mode register, all other combinations
of BA0-BA1 are reserved.)
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A8 (x16) or A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while
A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).For x16: LDQM controls
DQ0-DQ7 and UDQM controls DQ8-DQ15. For x32: DQM0 controls DQ0-7, DQM1 controls DQ8-15, DQM2 controls DQ16-
23, and DQM3 controls DQ24-31.
Table 8:
Truth Table–Commands and DQM Operation
(Note: 1)
NAME (FUNCTION)
CS#
RAS# CAS#
WE#
DQM
ADDR
DQS
NOTES
COMMAND INHIBIT (NOP)
HX
X
NO OPERATION (NOP)
L
HHH
X
ACTIVE (Select bank and activate row)
L
H
X
Bank/Row
X
3
READ (Select bank and column, and start READ burst)
LH
L
H
L/H8
Bank/Col
X
4
WRITE (Select bank and column, and start WRITE burst)
LH
L
L/H8
Bank/Col
Valid
4
BURST TERMINATE
LH
H
L
X
Active
PRECHARGE (Deactivate row in bank or banks)
LLHL
X
Code
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LL
L
H
X
6, 7
LOAD MODE REGISTER
L
X
Op-Code
X
2
Write Enable/Output Enable
––
–
L
–
Active
8
Write Inhibit/Output High-Z
–
H
–
High-Z
8
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