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參數(shù)資料
| 型號： | MT48LC8M8A2TG-8EL:GIT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 17/55頁 |
| 文件大?。?/td> | 1454K |
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24
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
Figure 22
Clock Suspend During WRITE Burst
Figure 23
Clock Suspend During READ Burst
CLOCK SUSPEND
The clock suspend mode occurs when a column ac-
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the in-
put pins at the time of a suspended internal clock edge
is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in
Figures 22 and 23.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the pro-
grammed burst length and sequence, just as in the
normal mode of operation (M9 = 0).
DON’T CARE
DIN
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
n
NOP
CLK
T2
T1
T4
T3
T5
T0
CKE
INTERNAL
CLOCK
NOP
DIN
n + 1
DIN
n + 2
TRANSITIONING DATA
DON’T CARE
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
CKE
INTERNAL
CLOCK
NOP
TRANSITIONING DATA
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| MT48LCM32B2P | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SDR SDRAM MT48LC2M32B2 a?? 512K x 32 x 4 Banks |
| MT48NN | 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
| MT48NNX | 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
| MT48NS | 功能描述:插線板 1 RU PANEL 48 LF JA RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
| MT48NSX | 功能描述:插線板 1/4" LF SLDR BAY 1RU, 2X24, NORM STR RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
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