參數(shù)資料
型號(hào)： MT48LC8M8A2TG-8EL:GIT
元件分類： DRAM
英文描述： 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 8/55頁(yè)
文件大?。?/td> 1454K
16
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 7 for CAS latencies of two
and three; data element n + 3 is either the last of a burst
of four or the last desired of a longer burst. The 64Mb
SDRAM uses a pipelined architecture and therefore
Figure 7
Consecutive READ Bursts
does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
DON’T CARE
NOTE: Each READ command may be to any bank. DQM is LOW.
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
BANK,
COL b
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
READ
X = 1 cycle
CAS Latency = 2
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
BANK,
COL b
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
READ
NOP
T7
X = 2 cycles
CAS Latency = 3
TRANSITIONING DATA
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