參數(shù)資料
型號(hào)： MT48V4M32TG-8XT
元件分類： DRAM
英文描述： 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 11/69頁(yè)
文件大?。?/td> 6213K
代理商： MT48V4M32TG-8XT
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
19
2001 Micron Technology, Inc. All rights reserved.
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) refresh in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a
refresh is required. All active banks must be PRE-
CHARGED prior to issuing an AUTO REFRESH com-
mand. The AUTO REFRESH command should not be
issued until the minimum tRP has been met after the
PRECHARGE command as shown in the operation sec-
tion.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 128Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (tREF), regardless of width option. Providing a
distributed AUTO REFRESH command every 15.625s
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (tRFC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care” with the
exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform
its own auto refresh cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
tRAS and may remain in self refresh mode for an indef-
inite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable (sta-
ble clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks, regardless of clock frequency) for tXSR because
time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 15.625s or less as
both SELF REFRESH and AUTO REFRESH utilize the
row refresh counter.
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