參數(shù)資料
型號: MT4JSF6464HIY-80BXX
元件分類: DRAM
英文描述: 64M X 64 DDR DRAM MODULE, ZMA204
封裝: LEAD FREE, SODIMM-204
文件頁數(shù): 7/19頁
文件大小: 618K
代理商: MT4JSF6464HIY-80BXX
PDF: 09005aef82b2f090/Source: 09005aef82b2f012
Micron Technology, Inc., reserves the right to change products or specifications without notice.
JSF4C64_64x64HY.fm - Rev. B 3/08 EN
15
2007 Micron Technology, Inc. All rights reserved
512MB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Temperature Sensor with Serial Presence-Detect EEPROM
Configuration Register
Table 16:
Capability Register Bit Descriptions
Bit
Description
0
Basic capability
1: Has alarm and critical trip point capabilities
1Accuracy
0: ±2°C over the active range and ±3°C over the monitor range
1: ±1°C over the active range and ±2°C over the monitor range
2Wider range
0: Temperatures lower than 0°C are clamped to a binary value of 0
1: Temperatures below 0°C can be read
4:3
Temperature resolution
00: 0.5°C LSB
01: 0.25°C LSB
10: 0.125°C LSB
11: 0.0625°C LSB
15:5
0: Must be set to zero
Table 17:
Configuration Register (Address: 0x01)
Bit
15
14
13
12
11
10
9
8
RFU
Hysteresis
Shutdown
mode
Bit
7
6
5
4
3
2
1
0
Critical lock
bit
Alarm lock bit
Clear event
Event output
status
Event output
control
Critical event
only
Event polarity
Event mode
Table 18:
Configuration Register Bit Descriptions
Bit
Description
Notes
0
Event mode
0: Comparator mode
1: Interrupt mode
Event mode cannot be changed if either of the lock bits
is set.
1
EVENT# polarity
0: Active LOW
1: Active HIGH
EVENT# polarity cannot be changed if either of the lock
bits is set.
2
Critical event only
0: EVENT# trips on alarm or critical temperature event
1: EVENT# trips only if critical temperature is reached
3
Event output control
0: Event output disabled
1: Event output enabled
4Event status
0: EVENT# has not been asserted by this device
1: EVENT# is being asserted due to an alarm window or
critical temperature condition
This is a read-only field in the register. The event
causing the event can be determined from the read
temperature register.
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