參數(shù)資料
型號(hào): MT58L128L36P1T-5
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 128K X 36 CACHE SRAM, 2.8 ns, PQFP100
封裝: PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù): 10/30頁(yè)
文件大?。?/td> 481K
代理商: MT58L128L36P1T-5
18
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOTE: 1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device
is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25°C, and 10ns cycle time.
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C
≤ T
A ≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMB O L TYP -4.4 -5
-6 -7.5 -10 UNITS NOTES
Power Supply
Device selected; All inputs
≤ VIL
Current:
or
≥ VIH; Cycle time ≥ tKC (MIN);
IDD
225 575 525 475 375 300
m A
2, 3, 4
Operating
VDD = MAX; Outputs open
Power Supply
Device selected; VDD = MAX;
Current: Idle
ADSC#, ADSP#, GW#, BWx#, ADV#
IDD1
55 130 120 110 90
85
m A
2, 3, 4
VIH; All inputs
≤ VSS + 0.2 or ≥ VDDQ - 0.2;
Cycle time
tKC (MIN)
CMOS Standby
Device deselected; VDD = MAX;
All inputs
≤ VSS + 0.2 or ≥ VDDQ - 0.2;
ISB2
0.4
10
m A
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; VDD = MAX;
All inputs
≤ VIL or ≥ VIH;ISB3
8
2525252525
m A
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
ISB4
55 130 120 110 90
85
m A
3, 4
VIH; All inputs
≤ VSS + 0.2 or ≥ VDDQ - 0.2;
Cycle time
tKC (MIN)
MAX
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