參數(shù)資料
型號: MT58L512Y36FT-8.5
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 512K X 36 CACHE SRAM, 8.5 ns, PQFP100
封裝: PLASTIC, TQFP-100
文件頁數(shù): 13/34頁
文件大?。?/td> 537K
代理商: MT58L512Y36FT-8.5
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03
20
2003 Micron Technology, Inc.
Figure 9:
READ/WRITE Timing
NOTE:
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following
A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
Q
ADV#
Single WRITE
D(A3)
A3
A4
D
BURST READ
Back-to-Back READs
(NOTE 5)
High-Z
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
tWH
tWS
tOEHZ
tDH
tDS
tKQ
tOELZ
(NOTE 1)
A1
A5
A6
D(A5)
D(A6)
Q(A1)
Back-to-Back
WRITEs
BWE#,
BWa#-BWd#
(NOTE 4)
DON’T CARE
UNDEFINED
(NOTE 3)
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