參數(shù)資料
型號(hào)： MT58L512Y36FT-8.5
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 512K X 36 CACHE SRAM, 8.5 ns, PQFP100
封裝： PLASTIC, TQFP-100
文件頁數(shù)： 7/34頁
文件大?。?/td> 537K
代理商： MT58L512Y36FT-8.5
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03
15
2003 Micron Technology, Inc.
Table 15:
3.3V VDD, IDD Operating Conditions and Maximum Limits
(1 Meg x 18 and 512K x 32/36)
Notes appear following parameter tables on page 17; 0C
TA +70C; VDD and VDDQ = 3.3V ±0.165V unless otherwise
noted
MAX
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-6.8
-7.5
-8.5
-10
UNITS
NOTES
Power Supply
Current:
Operating
Device selected; All inputs
VIL or
VIH; Cycle time tKC (MIN);
VDD = MAX; Outputs open
IDD
200
320
290
260
230
mA
Power Supply
Current: Idle
Device selected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#,
BWx#
VIH; All inputs VSS + 0.2
or
VDD - 0.2; Cycle time
tKC (MIN); Outputs open
IDD1
80
120
110
100
90
mA
CMOS Standby
Device deselected; VDD = MAX;
All inputs
VSS + 0.2 or
VDD - 0.2; All inputs static;
CLK frequency = 0
ISB2
8
30303030
mA
8, 9
Clock Running
Device deselected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#,
BWx#
VIH; All inputs VSS + 0.2
or
VDD - 0.2;
Cycle time
tKC (MIN)
ISB4
80
120
110
100
90
mA
8, 9
Snooze Mode
ZZ
VIH
ISB2Z
8
30303030
mA
Table 16:
2.5V VDD, IDD Operating Conditions and Maximum Limits
(1 Meg x 18 and 512K x 32/36)
Notes appear following parameter tables on page 17; 0C
TA +70C; VDD and VDDQ = 2.5V ±0.125V unless otherwise
noted
MAX
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-6.8
-7.5
-8.5
-10
UNITS
NOTES
Power Supply
Current:
Operating
Device selected; All inputs
VIL or
VIH; Cycle time tKC (MIN);
VDD = MAX; Outputs open
IDD
190
240
230
220
200
mA
Power Supply
Current: Idle
Device selected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#,
BWx#
VIH; All inputs VSS + 0.2
or
VDD - 0.2; Cycle time
tKC (MIN); Outputs open
IDD1
80
120
110
100
90
mA
CMOS Standby
Device deselected; VDD = MAX;
All inputs
VSS + 0.2 or
VDD - 0.2; All inputs static;
CLK frequency = 0
ISB2
8
30303030
mA
Clock Running
Device deselected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#,
BWx#
VIH; All inputs VSS + 0.2
or
VDD - 0.2;
Cycle time
tKC (MIN)
ISB4
80
120
110
100
90
mA
Snooze Mode
ZZ
VIH
ISB2Z
8
30303030
mA
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