參數(shù)資料
型號(hào): MT89L86AN
廠商: Mitel Networks Corporation
英文描述: CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch
中文描述: 意法半導(dǎo)體的CMOS總線⑩家庭多速率數(shù)字開(kāi)關(guān)
文件頁(yè)數(shù): 19/40頁(yè)
文件大?。?/td> 173K
代理商: MT89L86AN
Advance Information
MT89L86
19
Stream Pair Selection Register - Read/Write
Figure 7 - Stream Pair Selection (SPS) Register
x=Don’t care
Frame Input Offset Register - Read/Write
Figure 8 - Frame Input Offset (FIO) Register
x=Don’t care
Bit
5-3
Name
SPA2-0
Description
Stream Pair A selection
. These three bits define which pair of streams are going to be
connected to the switch matrix, together with the permanently connected streams
STi0-1 / STo0-1.
SPA2
SPA1
SPA0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Stream Pair B selection
. These three bits define which pair of streams are going to be
connected to the switch matrix, together with the permanently connected streams
STi0-1 / STo0-1.
SPB2
SPB1
SPB0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Stream Pair A Connected
STi2 / STo2
STi3 / STo3
STi4 / STo4
STi5 / STo5
STi6 / STo6
STi7 / STo7
STi8 / STo8
STi9 / STo9
2-0
SPB2-0
Stream Pair B Connected
STi2 / STo2
STi3 / STo3
STi4 / STo4
STi5 / STo5
STi6 / STo6
STi7 / STo7
STi8 / STo8
STi9 / STo9
These bits are only used when the Switching Configuration bits enable stream pair selection capability (SCB 1-0 =10) and the Input Data Rate
Selection bits enable 2 Mb/s operation (IDR-0 = 00). In all other modes, the contents of this register are ignored.
BIT
7-5
NAME
OFB2-0
DESCRIPTION
Offset Bits 2-0
. These three bits define the time it takes the Serial Interface receiver to
recognize and store the first bit of the serial input streams; i.e., to start assuming a new
internal frame. The input frame offset can be selected to be up to 4 CK clock periods from
the time when frame pulse input signal is applied to the FR input.
OFB2
OFB1
OFB0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
If frame input offset operation is not required, this register should be cleared by the CPU during system initialization.
Number of Clock Periods
Normal Operation. No bit offsetting.
1
2
3
4
Reserved
Reserved
Reserved
X
X
SPA2
SPA1
SPA0
SPB2
SPB1
SPB0
7
6
5
4
3
2
1
0
OFB2
OFB1
OFB0
X
X
X
X
X
7
6
5
4
3
2
1
0
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