- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383644 > MT89L86AN (Mitel Networks Corporation) CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch PDF資料下載
參數(shù)資料
| 型號： | MT89L86AN |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch |
| 中文描述： | 意法半導體的CMOS總線⑩家庭多速率數(shù)字開關(guān) |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 173K |
| 代理商： | MT89L86AN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Advance Information
MT89L86
9
When the input frame offset is enabled, an "internal
delay" of up to four clock periods is added to the
actual data input sampling, providing the MT89L86
serial timing unit a new input frame reference. An
internal virtual frame is created which is aligned with
the framing of the actual serial data coming in at the
serial inputs and not with the FR frame pulse input.
In this operation, the transmission of the output
frame on the serial links is still aligned to the frame
pulse input signal (FR).
The selection of the data input sampling delay is
defined by the CPU in the Frame Input Offset
Register (FIO). If this function is not required in the
user's applications, the FIO register should be set up
during system initialization to a state where offset
functions are disabled.
Delay Through the MT89L86
The switching of information from the input serial
streams to the output serial streams results in a
delay. Depending on the type of information to be
switched, this MT89L86 can be programmed to
perform time-slot interchange functions with different
throughput delay capabilities on a per-channel basis.
For voice applications, variable throughput delay can
be selected ensuring minimum delay between input
and output data. In wideband data applications,
constant
throughput
delay
maintaining the frame integrity of the information
through the switch.
can
be
selected
The delay through the device varies according to the
type of throughput delay selected in the V/C bit of the
connect memory high.
Variable Throughput Delay Mode (V/C bit = 0)
Identical I/O Data Rates
The delay in this mode is dependent on the
combination of source and destination channels and
it is independent of the input and output streams.
The minimum delay achievable in this MT89L86
depends on the data rate selected for the serial
streams. For instance, for the 2.048 Mb/s data rate,
the minimum delay achieved corresponds to three
time-slots. For the 4.096 Mb/s data rate it
corresponds to five time-slots while it is nine time-
slots for the 8.192 Mb/s data rate. Switching
Table 3a - Variable Throughput Delay Values for Identical I/O Rate Applications
n= input channel, t.s. = time-slot
Table 3b - Min/Max Throughput Delay Values for Different I/O Rate Applications
Notes:
dmin and dmax are measured in time-slots and at the point in time when the output channel is completely shifted out.
t.s. = time-slot
fr. = 125
μ
s frame
2 Mb/s t.s. = 3.9
μ
s
4 Mb/s t.s. = 1.95
μ
s
8 Mb/s t.s. = 0.975
μ
s
Input Rate
Output Channel (# m)
m < n
m=n, n+1, n+2
m= n+3, n+4
m=n+5, .. n+8
m > n+8
2.048 Mb/s
32-(n-m) t.s.
m-n + 32 t.s.
m-n t.s.
m-n t.s.
m-n t.s.
4.096 Mb/s
64-(n-m) t.s.
m-n + 64 t.s.
m-n+64 t.s.
m-n t.s.
m-n t.s.
8.192 Mb/s
128-(n-m) t.s.
m-n + 128 t.s.
m-n+128 t.s.
m-n+128 t.s.
m-n t.s.
I/O Data Rate
Configuration
Output Stream Used
0, 1
2, 3
4, 5
6, 7
2 Mb/s to 4 Mb/s
dmin=5x 4Mb/s t.s.
dmax=1 fr.+(4x 4Mb/s t.s.)
2 Mb/s to 8 Mb/s
dmin=9x 8Mb/s t.s.
dmax=1 fr.+(8x 8Mb/s t.s.)
4 Mb/s to 2 Mb/s
dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
8 Mb/s to 2 Mb/s
dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s
t.s.)
dmin=(2x 2Mb/s t.s.)+
(3x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(3x 8Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+
(2x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(2x 8Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+
(1x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(1x 8Mb/s t.s.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT89L86AP | CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch |
| MT90210 | Multi-Rate Parallel Access Circuit(并行多路存取電路) |
| MT90210 | Multi-Rate Parallel Access Circuit |
| MT90210AL | Multi-Rate Parallel Access Circuit |
| MT90220 | Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT89L86AN1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 3.3V 4 - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 48SSOP 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 48SSOP |
| MT89L86ANR1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 3.3V 4 - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 48SSOP 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 48SSOP |
| MT89L86AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch |
| MT89L86AP1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 3.3V 4 - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC |
| MT89L86APR1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 3.3V 4 - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復。