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參數(shù)資料
| 型號： | MT90520AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA456 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-456 |
| 文件頁數(shù)： | 58/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520AG |
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MT90520
Data Sheet
58
Zarlink Semiconductor Inc.
4.5.2 UDT Mode of Operation
In the UDT mode of operation, the TX_SAR is capable of generating and transmitting cells for 8 independent VCs,
representing each of the 8 TDM ports of the MT90520 device.
4.5.2.1 Control Structure Configuration
The first step in setting up the TX_SAR for UDT operation is the configuration of a UDT Segmentation Control
Structure, as shown in Figure 20.
There must be one control structure for each UDT VC that the TX_SAR is to transmit. A control structure may be
located at any address within the internal memory space which is reserved for Segmentation Control Structures
(starting at byte address 80000h). The TX_SAR hardware identifies the location of a particular control structure by
reading the TX_SAR Pointer Table Base Register for the corresponding TDM port. These registers are located at
byte addresses 1000h + p*2h, where p represents the particular port number. Within these registers, the user must
configure the least-significant 14 bits to point to the word address of the start of a UDT Segmentation Control
Structure in internal memory. As well, the TXCFG bits in the register must be set to “01” to indicate that the control
structure being pointed to is formatted for UDT transmission.
Figure 20 - Segmentation Control Structure - UDT Format
All of the fields within the control structure are explained in the text accompanying Figure 20. Upon initialization,
several of the fields within the UDT Segmentation Control Structure need to be explicitly configured by the user. The
GFC
,
VPI
, and
VCI
fields must be programmed to configure the header of the outgoing cells to contain the correct
routing information. The user may also program the
PTI
and
CLP
fields to configure the networking properties for
the cells on the VC. Additionally, the user can configure the
HEC
and
UDF2
fields of outgoing cells. The
HEC
field
is used primarily as a place-holder since PHY devices are usually responsible for the generation of header error
checking values. The value contained in the
UDF2
field is only transmitted in outgoing cells if the MT90520 is using
a 16-bit UTOPIA interface. If the VC is going to be carrying RTS nibbles, the
SE
bit must be set, as detailed in the
figure above. The remaining fields in the control structure should be cleared upon initialization.
Once the control structure has been configured, the transmission of CBR cells can begin as soon as the TX_SAR is
enabled, by setting the TXENB bit in the TX_SAR Master Enable Register at byte address 1044h.
SRTS:
If
SE
is set, an RTS value is read from the Clock Management module at the
beginning of each cell sequence (i.e., sequence number = 0) and stored in this field.
In cells with odd sequence numbers, the MSB from this field is placed into the CSI bit
of the SAR-PDU header. The
SRTS
value is then shifted left. A complete RTS nibble
is sent in each 8-cell sequence.
SE (SRTS Enable):
When set, indicates that the VC is transmitting SRTS data.
When cleared, the CSI bit of outgoing cells is cleared to ‘0’.
SN (Sequence Number):
Sequence number of the next cell to be transmitted.
Should be initialized to “0” by software.
GFC:
The Generic Flow Control value is placed in the GFC field of the cell header in
a UNI cell. If the cell is using NNI formatting, these bits hold the four MSB of the VPI.
VPI:
This value is placed in the VPI field of outgoing cell headers.
VCI:
This value is placed in the VCI field of outgoing cell headers.
PTI:
This value is placed in the PTI field of the generated cell headers.
C (CLP):
This value is placed in the CLP field of outgoing cell headers.
HEC:
This value is placed in the HEC field of outgoing cell headers. The physical
layer is generally responsible for calculating HEC values; therefore, this field is used
as a place holder. If the physical layer does not calculate the HEC, the user may
generate the appropriate HEC value by performing a modulo-2 division of the first
four octets of the cell header using the generator polynomial G(x) = x
8
+ x
2
+ x + 1.
UDF2:
This value is placed in the UDF2 field of the cell header when the UTOPIA
interface is operating in 16-bit mode.
Cell Count Statistic:
Rollover counter which counts the number of cells transmitted
on this VC by the TX_SAR module. Should be initialized to “0” by software.
Note 1:
Fields which appear in dark grey are reserved fields
which must be cleared by software upon initialization.
Note 2
: Fields which appear in light grey are those which are
updated by hardware.
+00
Byte
Add
+00
Word
Add
0
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SN
GFC
VPI
VCI
VCI
PTI
C
HEC
UDF2
Cell Count Statistic
+02
+04
+08
+06
+01
+02
+03
+04
Reserved
SRTS
S
E
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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