參數資料
型號： MT90520AG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數字傳輸電路
英文描述： 8-Port Primary Rate Circuit Emulation AAL1 SAR
中文描述： ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA456
封裝： 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-456
文件頁數： 74/180頁
文件大小： 1736K
代理商： MT90520AG
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MT90520
Data Sheet
74
Zarlink Semiconductor Inc.
sync
late cell timeout period reached and
CHECK_LATE_ARRIVALS = ‘1’
- UDT RX_SAR inserts a single
dummy cell
late_cell_insertion
invalid sequence number
- accept received cell
invalid
received cell is in sequence with previous cell
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell is not in sequence with the
previously-received cell -> received cell has a
sequence number one greater than the
expected sequence number
- assume single-cell loss event
- UDT RX_SAR inserts a single
dummy cell
- after dummy cell insertion, accept
received cell (in-order dummy cell
insertion)
- declare
aal1_seq_error
single_cell_loss_
misinsertion
received cell is not in sequence with the
previously-received cell -> received cell has a
sequence number that is NOT one greater
than the expected sequence number
- cannot assume what happened
(may be a multi-cell loss case)
- accept received cell (thus, if this is
a multi-cell loss case, out-of-order
dummy cell insertion will occur)
- declare
aal1_seq_error
out_of_seq
invalid
invalid sequence number
- discard cell
start
received cell is in sequence with last “good”
cell (i.e., cell misinsertion)
- discard cell
- declare
misinserted_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell has a valid sequence number
that is two greater than the last “good” cell
(i.e., sequence number protection failure)
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell has valid sequence number, but
doesn’t meet either of the 2 previous criteria
- discard cell
out_of_sync
out_of_seq
invalid sequence number
- discard cell
start
received cell is in sequence with last received
cell (i.e., multiple cell loss)
- calculate number of lost cells (up
to 7)
- UDT RX_SAR inserts dummy
cell(s)
- after dummy cell insertion(s),
accept received cell
- declare
lost_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell has a valid sequence number
that is two greater than the last in-sequence
cell (i.e., sequence number protection failure)
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell has valid sequence number, but
doesn’t meet either of the 2 previous criteria
Table 15 - Operation of UDT Fast Sequence Number Processing State Machine
- discard cell
out_of_sync
Current State
Transition Event
Action Taken
Next State
Note
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相關代理商/技術參數
參數描述
MT90520AG2 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays
MT90528 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
MT90528AG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
MT90528AG2 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
MT90710 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer
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