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參數(shù)資料
| 型號(hào)： | MT90520AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA456 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-456 |
| 文件頁(yè)數(shù)： | 69/180頁(yè) |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520AG |
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MT90520
Data Sheet
69
Zarlink Semiconductor Inc.
SDT Control Structure Fields - Initialization
As in the UDT case, upon initialization, only a few of the fields within the SDT Reassembly Control Structure need
to be explicitly configured by the user. The fields which must be configured are listed below. Details of the
appropriate values for configuration can be found in Table on page 70.
Maximum Lead
must be configured to a value which accounts for the expected CDV of the network, and the
desired distance to be maintained between the SDT RX_SAR’s write pointer and the TDM module’s read
pointer. More details regarding the programming of Maximum Lead are given within the section “SDT
Reassembly Circular Buffers” on page 81.
If all of the data within the VC is destined for the same TDM port,
VC TDM Port
must be configured to match
the desired destination port for the VC’s data. However, if the data is destined for multiple ports (trunking),
this field must be configured to match the port whose TDM read pointer will be used for slip-checking and
clock recovery.
First Entry
must always be set to 0Eh.
Last Entry
must be programmed to the word-address of the last
Reassembly Circular Buffer Base Address within the control structure.
If SRTS or Adaptive clock recovery methods are to be employed on this VC, the appropriate configuration bit
(either
S
or
A
) must be set.
The
M (Multiframe Type)
bit is used to select either DS1 (‘0’) or E1 (‘1’) multiframing format for use when
the VC is carrying CAS signalling bits. If “basic” SDT mode is being used, the value of this field does not
matter.
Structure Length
must contain the length (less one) of the AAL1 structure size for this VC, including both
TDM and CAS bytes.
The
CAS
field must be configured if the VC being received is carrying CAS signalling nibbles.
The
BS
field should be set to the desired size of the SDT Reassembly Circular Buffers for the VC. The
configurable buffer sizes range from 64 entries to 1024 entries per channel. Note that all of the channels
within the VC are allocated the same size buffers in external memory. It should also be noted that the size of
the buffers must correspond to the size field given within the TDM SDT Reassembly Control Structure for the
chosen TDM channel destination (port and channel specific), as shown in Figure 13 on page 46.
Number of Channels
must be set to the number of channels in the VC, less one (therefore, allowable
values for the field are 00h to 7Fh).
The
Pi (Pointer Initialization)
bit within the SDT Reassembly Control Structure
must
be set to ‘1’, indicating
that the control structure is ready to start receiving pointers.
Current Entry
must be programmed to contain the value in the First Entry field (i.e., 0Eh).
The
Reassembly Circular Buffer Base Address
fields must contain the values of the word-addresses of
the corresponding circular buffers in external memory. A two-bit value, the Reassembly Circular Buffer Base
Address, is obtained from the CB_BASE_ADD field of the SDT Reassembly Control Register at byte-
address 2040h. These bits form the two most significant bits of a word-address formed by concatenating
these bits with the 12-bit value obtained from the Reassembly Circular Buffer Base Address. Which bits of
the concatenated address are used to form the actual address to external memory is determined by the size
of the buffers selected for the VC. For details regarding how these addresses are formed, See “SDT
Reassembly Circular Buffers” on page 81., particularly Table 18. It should be noted that the Reassembly
Circular Buffer Base Address must correspond to the address given within the TDM SDT Reassembly
Control Structure for the chosen TDM channel destination (port and channel specific), as shown in Figure 13
on page 46.
The
CASx
field for each channel in the VC (where
x
represents the channel within the VC) should be cleared
if the VC is not carrying CAS. However, if the VC is programmed to receive CAS nibbles, software can
configure these nibbles to contain any values desired by the user. The software-programmed values within
these fields will be transferred to the TDM module (and therefore output on CSTo) until valid CAS nibbles
have been extracted from received cells.
All of the remaining fields within the SDT Reassembly Control Structure
must
be cleared to ‘0’ upon initialization.
This ensures that the initialization, statistics, and status fields for the VC are configured to start with cleared values.
相關(guān)PDF資料 |
PDF描述 |
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| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
| MT90820AL | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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