
MT9072
Data Sheet
86
Zarlink Semiconductor Inc.
c)
Local and Remote Timeslot Loopback
. Remote timeslot loopback control bit RTSL = 0 normal; RTSL = 1
activate, will loop around transmit ST-BUS timeslots to the DSTo stream. Local timeslot loopback bits LTSL = 0
normal; LTSL = 1 activate, will loop around receive PCM30 timeslots towards the remote PCM30 end.
d)
Framer Remote loopback
- Internally connects RPOS and RNEG of one framer to TPOS and TNEG respectively
of one of the other integrated framers.
Bit RLBK01, RLBK23, RLBK45, RLBK67 = 0 normal; = 1 activate.
8 Mbit/s mode:
Bit RLBK8 = 0 normal; = 1 activate.
e)
Framer ST-BUS loopback
- Internally connects DSTi of one framer to DSTo of one of the other integrated
framers.
Bit SLBK01, SLBK23, SLBK45, SLBK67 = 0 normal; = 1 activate.
8 Mbit/s mode:
Bit SLBK8 = 0 normal; = 1 activate.
MT9072
Tx
DSTi
DSTo
System
PCM30
Rx
MT9072 Framer 0,2,4,6
Tx
DSTo
System
PCM30
Rx
DSTi
MT9072 Framer 1,3,5,7
DSTo
System
DSTi
Tx
Rx
MT9072 Framer 0-3
Tx
DSTo[0]
System
PCM30
Rx
DSTi[0]
MT9072 Framer 4-7
DSTo[4]
System
DSTi[4]
Tx
Rx
MT9072 Framer 0,2,4,6
Tx
DSTo
System
PCM30
Rx
DSTi
MT9072 Framer 1,3,5,7
DSTo
DSTi
Rx
Tx
PCM30
MT9072 Framer 0-3
Tx
DSTo[4]
System
PCM30
Rx
DSTi[0]
MT9072 Framer 4-7
DSTo[0]
DSTi[4]
Rx
Tx
PCM30