- 您現(xiàn)在的位置：買賣IC網 > PDF目錄383644 > MT90732AP (Mitel Networks Corporation) Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號： | MT90732AP |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 61K |
| 代理商： | MT90732AP |
Advance Information
CMOS
MT90732
5-19
Note: I = Input; O = Output; P = Power
47
WR
I
Write.
An active low signal generated by the microprocessor for writing to the
registers which reside in the memory map.
48
RDY
O
Ready.
An active high signal indicating an E2/E3F acknowledgment to the
microprocessor that the addressed memory map location can complete the
data transfer.
Control Interface
Pin #
Name
I/O/P
Description
13
NRZLINE
I
Non-Return to Zero Line Selection.
A high enables an NRZ line input (RP
and TP), and causes the HDB3 decoder/encoder to be bypassed. When low
enables the dual rail interface (RP/RN and TP/TN) and the HDB3
decoder/encoder.
14
BIP-4
I
Bit Interleaved Parity - 4.
A high enables the BIP-4 function. In the transmit
direction, the BIP-4 is calculated for data nibbles only, and is sent as the last
nibble in the frame format. In the receive direction, the BIP-4 is calculated for
the data bits only and compared against the received value which is present in
the last four bits of the frame. An output indication (BIP-4E) occurs when one
or more columns do not match.
16
15
M1
M0
I
Mode Control.
The two controls select the operating rate of the E2/E3F
according to the table given below.
19
MICRO
I
Microprocessor Mode.
A high enables the microprocessor interface. When
the microprocessor is enabled, the following hardware control leads are dis-
abled. BIP-4, Mode (M0 and M1), Serial I/O (SER), and transmit AIS (TAIS).
Bits are provided in the memory map for controlling these functions.
20
SER
I
Serial Interface.
A high selects the bit-serial interface for the terminal side
interface. A low selects the nibble-parallel interface.
21
TLBK
I
Terminal Loopback.
A low enables a transmit to receive loopback at the line
side.
22
PLBK
I
Payload Loopback.
A low enables a receive to transmit loopback at the termi-
nal side in the serial mode of operation only.
23
TAIS
I
Transmit Alarm Indication Signal.
A low causes an all ones signal (AIS) to
be sent in place of a G.7XX frame format.
24
LPT
I
Loop Timing.
A low enables the loop timing feature. Loop timing disables the
transmit clock and enables the receive clock to be used as the transmit clock.
26
FORCEFE
I
Force Framing Error.
The errored bit is sent into the framing pattern upon the
high-to-low transition of this pin.
Microprocessor Interface
Pin #
Name
I/O/P
Description
M1
M0
Recommendation
Rate (kbit/s)
0
0
G.745
8448
0
1
G.742
8448
1
0
G.753
34368
1
1
G.751
34368
相關PDF資料 |
PDF描述 |
|---|---|
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9074 | T1/E1/J1 Single Chip Transceiver |
| MT9074AL | T1/E1/J1 Single Chip Transceiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90733 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS DS3 Framer (DS3F) |
| MT90733AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS DS3 Framer (DS3F) |
| MT9074 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver |
| MT9074_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver |
| MT9074AL | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。