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參數(shù)資料
| 型號： | MT9075 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 95K |
| 代理商： | MT9075 |
Application Note
MSAN-174
3
3.0 System Implementation
Figure 3 illustrates a typical implementation of the
access network with a V5 interface. The user ports
can be POTs, ISDN BA or ISDN PRA. The number of
ports per card depends on the system requirements.
The back plane can be designed to accommodate
any type of user port cards (POTs, ISDN BA, ISDN
PRA etc.) providing maximum configuration flexibility.
Common centralized resources such as the
switching,
concentration
generation can reside on the same card resulting in
further cost savings.
and
system
clock
3.1 Local exchange interface
This section describes the physical level interface
between the AN and the LE. Layer 1 consists of a
single (for V5.1) or up to 16 (for V5.2) 2.048Mb/s E1
links as specified by G.703, G.704 and G.706.
An E1 interface, from the functional viewpoint, is
composed of two parts: a framer to support all layer
1 requirements per G.704 and G.706; and a line
interface unit (LIU) to drive the physical line which is
either twisted pair or coaxial cable.
The MT9075, a single chip E1 interface integrating
both framer and LIU, is the recommended Mitel
device for E1 implementation. It provides extensive
features for data link access, alarms, interrupts,
loopbacks and diagnostics, which makes it quite
suitable for V5 applications. Table 1 lists some
requirements of V5 on the physical and data link
layers, along with the MT9075 features that fulfill the
requirements. Another option to meet the same
requirements, is the single chip E1/T1 transceiver
MT9074.
The built-in Jitter Attenuator (JA), comprising a DPLL
and data FIFO, has several modes of operation
suitable for different conditions. Figure 4a shows the
operation of Line Synchronous mode in which the
timebase is synchronized to the received data
stream. The 2.048MHz clock E2o extracted from the
receive data is dejittered by the FIFO and then fed
into DPLL as the reference. The DPLL then
generates clean clocks to output on /C4b and /F0b
pins. If the E2o is lost due to link failure, the DPLL
automatically turns itself into free run mode to
maintain the constant supply of the /C4b and /F0b.
Figure 4b and 4c are System Bus Synchronous
modes in which /C4b and /F0b become input signals
as the reference to DPLL. The received PCM 30 data
is clocked into a slip buffer with the E2o and is
clocked out of the slip buffer with the /C4b. The jitter
and wander between /C4b and E2o, if any, is
absorbed by this 2-frame slip buffer. In System Bus
Synchronous modes the user can put the JA on
either receive path as Figure 4b, or transmit path as
Figure 4c, depending on the location of jitter source.
These are called as SysBusSync1 mode and
SysBusSync2 mode, respectively.
In the case of V5.1 with a single E1 link between the
AN and LE, it is suggested the JA be set in Line
Synchronous mode as shown in Figure 4a. The JA
meets both jitter transfer and jitter tolerance
characteristics as specified by G.823.
In the case of V5.2 with multiple E1 links (or multiple
V5.1 links between AN and LE) there are two
possible timing schemes available using MT9075
Figure 3 - A Typical System Implementation of the Access Network
Back
Plane
I/F
Switching
&
Concentration
System Cocks
Resources
Back
Plane
I/F
E1 Interface
E1 Interface
E1 Interface
*
*
Back
Plane
I/F
*
*
SLIC
SLIC
SLIC
SLIC
Codec
Codec
Codec
Codec
TDM
Bus
Control
Bus
Back
Plane
I/F
*
*
U Interface
U Interface
U Interface
U Interface
*
*
*
Centralized Resources
LE Interface
User Ports
Back Plane
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076AB | T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器) |
| MT9079 | Advanced Controller for E1(先進(jìn)的E1幀調(diào)節(jié)器和控制器) |
| MT9080B | SMX - Switch Matrix Module(用于消費類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9075A | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
| MT9075B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:E1 Single Chip Transceiver |
| MT9075B-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver |
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