參數(shù)資料
型號： MT9075AP
廠商： Mitel Networks Corporation
英文描述： E1 Single Chip Transceiver
中文描述： 素E1單芯片收發(fā)器
文件頁數(shù)： 58/78頁
文件大?。?/td> 1008K
代理商： MT9075AP
MT9075A
Preliminary Information
4-186
Table 83 - HDLC Control Register 1
(Page 0BH &0CH, Address 13H) (continued)
Table 83 - HDLC Control Register 1
(Page 0BH &0CH, Address 13H)
Table 84 - HDLC Status Register
(Pages 0BH & 0CH, Address 14H) (Continued)
Bit
Name
Functional Description
7
Adrec
Address Recognition.
When one
this
bit
will
recognition.
This
receiver to recognize only those
packets having the unique address
as programmed in the Receive
Address Recognition Registers or if
the address is an All call address.
enable
address
forces
the
6
RxEN
Receive Enable.
When one the
receiver will be immediately enabled
and will begin searching for flags,
Go-Aheads etc.
When zero this bit will disable the
HDLC receiver after the rest of the
packet presently being received is
finished. The receiver internal clock
is disabled.
5
TxEN
Transmit Enable.
When one the
transmitter will be immediately
enabled and will begin transmitting
data, if any, or go to a mark idle or
interframe time fill state.
When zero this bit will disable the
HDLC
transmitter
completion of the packet presently
being transmitted. The transmitter
internal clock is disabled.
after
the
4
EOP
End Of Packet.
Forms a tag on the
next byte written the TX FIFO, and
when set will indicate an end of
packet byte to the transmitter, which
will transmit an FCS following this
byte. This facilitates loading of
multiple packets into TX FIFO.
Reset automatically after a write to
the TX FIFO occurs.
3
FA
Frame Abort.
Forms a tag on the
next byte written to the TX FIFO,
and when set to one FA will indicate
to the transmitter that it should abort
the packet in which that byte is
being
transmitted.
automatically after a write to the TX
FIFO.
Reset
Bit
Name
Functional Description
2
Mark-Idle When zero, the transmitter will be in
an idle state. When one it is in an
interframe time fill state. These two
states will only occur when the TX
FIFO is empty.
1-0
RSV
Reserved: Must be set to 0 for
normal operation.
Bit
Name
Functional Description
7
Intgen
Interrupt Generation.
Intgen is set
to
1
when
an
conjunction with the Interrupt Mask
Register) has been generated by
the HDLC. This is an asynchronous
event. It is reset when the Interrupt
Register is read.
interrupt
(in
6
Idle Chan
Idle Channel.
This bit is set to a 1
when an idle Channel state (15 or
more ones) has been detected at
the
receiver.
asynchronous
becomes valid after the first 15 bits
or the first zero is received.
This
event.
is
an
Status
5, 4 RQ9, RQ8 Byte Status bits from RX FIFO.
These bits determine the status of
the byte to be read from RX FIFO
as follows:
RQ9
RQ8
Byte Status
0
0
Packet byte.
0
1
First byte.
1
0
Last byte of a good
packet.
1
1
Last byte of a bad
packet.
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