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參數(shù)資料
| 型號： | MT9075AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | E1 Single Chip Transceiver |
| 中文描述： | 素E1單芯片收發(fā)器 |
| 文件頁數(shù)： | 59/78頁 |
| 文件大?。?/td> | 1008K |
| 代理商： | MT9075AP |
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Preliminary Information
MT9075A
4-187
Table 84 - HDLC Status Register
(Pages 0BH & 0CH, Address 14H)
Bit
Name
Functional Description
3, 2
Txstat2,
Txstat1
Transmit
indicate the status of the TX FIFO
as follows:
Status.
These
bits
Txsta
t2
Txsta
t1
TX FIFO Status
0
0
TX FIFO full up to
the selected status
level or more. See
Table 93.
0
1
The number of bytes
in the TX FIFO has
reached
exceeded
selected
threshold level. See
Table 94.
or
the
interrupt
1
0
TX FIFO empty.
1
1
The number of bytes
in the TX FIFO is
less
than
selected
threshold level. See
Table 94.
the
interrupt
1, 0
Rxstat2,
Rxstat1
Receive
indicate the status of the RX FIFO
as follows:
Status.
These
bits
Rxsta
t2
Rxsta
t1
RX FIFO Status
0
0
RX FIFO empty.
0
1
The number of bytes
in the RX FIFO is
less
than
selected
level. See Table 94.
the
threshold
1
0
RX FIFO full up to
the selected status
level or more. See
Table 93.
1
1
The number of bytes
in the RX FIFO has
reached
exceeded
selected
threshold level. See
Table 94.
or
the
interrupt
Bit
Name
Functional Description
7
Intsel
Interrupt Selection.
When one, this
bit will cause bit 2 of the Interrupt
Register to reflect a TX FIFO
underrun (TXunder). When zero,
this interrupt will reflect a frame
abort (FA).
6
Cycle
When one, this bit will cause the
transmit byte count to cycle through
the value loaded into the Transmit
Byte Count Register.
5
Tcrci
Transmit CRC Inhibited
. When
one, this bit will inhibit transmission
of the CRC. That is, the transmitter
will not insert the computed CRC
onto the bit stream after seeing the
EOP tag byte. This is used in V.120
terminal adaptation for synchronous
protocol sensitive UI frames.
4
Seven
Seven Bits Address Recognition.
When one, this bit will enable seven
bits of address recognition in the
first address byte. The received
address byte must have bit 0 equal
to 1 which indicates a single
address byte is being received.
3
RSV
Reserved, must be zero for normal
operation.
2
RSV
Reserved, must be zero for normal
operation.
1
Rxfrst
RX FIFO Reset
. When one, the RX
FIFO will be reset. This causes the
receiver to be disabled until the next
reception of a flag. The status
register will identify the FIFO as
being empty. However, the actual
bit values in the RX FIFO will not be
reset.
0
Txfrst
TX FIFO Reset.
When one, the TX
FIFO will be reset. The Status
Register will identify the FIFO as
being empty. This bit will be reset
when data is written to the TX FIFO.
However, the actual bit values of
data in the TX FIFO will not be
reset. It is cleared by the next write
to the TX FIFO.
Table 85 - HDLC Control Register 2
(Pages 0BH & 0CH, Address 15H)
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| MT9075BP | 制造商:Microsemi Corporation 功能描述: |
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