參數(shù)資料
型號: MT9092
廠商: Mitel Networks Corporation
英文描述: Digital Telephone with HDLC(數(shù)字電話(帶高階數(shù)據(jù)鏈路控制HDLC))
中文描述: 數(shù)字電話(數(shù)字電話(帶高階數(shù)據(jù)鏈路控制的HDLC)與的HDLC)
文件頁數(shù): 17/44頁
文件大小: 278K
代理商: MT9092
MT9092
7-19
The data streams operate at 2048kb/s and are Time
Division Multiplexed into 32 identical channels of
64kb/s bandwidth. Frame Pulse (a 244nSec low
going pulse) is used to parse the continuous serial
data streams into the 32 channel TDM frames. Each
frame has a 125
μ
Second period translating into an 8
kHz frame rate. Valid frame pulse occurs when F0i is
logic low coincident with a falling edge of C4i. C4i
has a frequency (4096MHz) which is twice the data
rate. This clock is used to sample the data at the 3/4
bit-cell position on DSTi and to make data available
on DSTo at the start of the bit-cell. C4i is also used
to clock the HPhone-
II
internal functions (i.e., DSP,
Filter/CODEC, HDLC) and to provide the channel
timing requirements.
The HPhone-
II
uses only the first 4 channels of the
32 channel frame. These channels are always
defined, beginning with the first channel after frame
pulse, as shown in Figure 7 (DSTi and DSTo channel
assignments). Channels are enabled independantly
by the four control bits Ch
0
En -Ch
3
En residing in the
Timing Control Register (address15h).
Ch
0
EN - D-Channel
Channel 0 conveys the D-Channel HDLC
information. Since this function is dedicated to
16kb/s operation, only the first two bits (LSB's)
of the octet are required; the remaining six bits
of the D-Channel octet carry no information and
are tri-stated. When CH
0
EN is high, HDLC data
is transmitted on DSTo. When low, DSTo is
forced to logic 0 for the two least significant bit
positions. Incoming DSTi data is always
routed to the HDLC block regardless of this
control bit's logic state.
Ch
1
EN - C-Channel
Channel
information for Mitel’s layer 1 transceiver. The
full 64kb/s bandwidth is available and is
assigned according to which transceiver is
being used. Consult the data sheet for the
selected transceiver for its bit definitions and
order of bit transfer. When this bit is high
register data is transmitted on DSTo. When low,
this timeslot is tri-stated on DSTo. Receive C-
Channel data (DSTi) is always routed to the
register regardless of this control bit's logic
state. C-channel data is transferred on the ST-
BUS MSB first by the HPhone-
II
.
1
conveys
the
control/status
Ch
2
EN and Ch
3
EN - B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels,
respectively. These bits (Ch
2
EN and Ch
3
EN)
are used to enable the PCM channels from/to
the HPhone-
II
as required.
Transmit PCM on DSTo
When high, PCM from the Filter/CODEC and DSP is
transmitted on DSTo in the selected ST-BUS
channel. When low, DSTo is forced to logic 0 for the
corresponding timeslot. If both Ch
2
EN and Ch
3
EN
are enabled, default is to channel 2.
Receive PCM from DSTi
When high, PCM from DSTi is routed to the DSP and
Filter/CODEC in the associated channel. If both
Ch
2
EN and Ch
3
EN are enabled the default is to
channel 2.
Figure 7 - ST-BUS Channel Assignment
F0i
DSTi,
DSTo
125
μ
s
CHANNEL 1
C-channel
CHANNEL 3
B2-channel
CHANNEL 2
B1-channel
CHANNELS 4 - 31
Not Used
MSB first for C, B1 - & B2-
Channels
CHANNEL 0
D-channel
LSB first
for D-
Channel
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