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參數資料
| 型號： | MT9122AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS Dual Voice Echo Canceller with Tone Detection |
| 中文描述： | CMOS雙語音回聲消除的音偵測 |
| 文件頁數： | 19/32頁 |
| 文件大小： | 143K |
| 代理商： | MT9122AP |
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Preliminary Information
MT9122
8-35
Power Reset Value
N/A
7
6
5
4
3
2
1
0
RP
15
RP
14
RP
13
RP
12
RP
10
RP
9
RP
8
RP
11
Echo Canceller A, Rin Peak Detect Register 2
Echo Canceller B, Rin Peak Detect Register 2
ADDRESS = 0Dh READ
ADDRESS = 2Dh READ
Power Reset Value
N/A
7
6
5
4
3
2
1
0
RP
7
RP
6
RP
5
RP
4
RP
2
RP
1
RP
0
RP
3
Echo Canceller A, Rin Peak Detect Register 1
Echo Canceller B, Rin Peak Detect Register 1
ADDRESS = 0Ch READ
ADDRESS = 2Ch READ
These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16-bit 2’s
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low
byte is in Register 1.
RP
RP
Power Reset Value
N/A
7
6
5
4
3
2
1
0
SP
15
SP
14
SP
13
SP
12
SP
10
SP
9
SP
8
SP
11
Echo Canceller A, Sin Peak Detect Register 2
Echo Canceller B, Sin Peak Detect Register 2
ADDRESS = 0Fh READ
ADDRESS = 2Fh READ
Power Reset Value
N/A
7
6
5
4
3
2
1
0
SP
7
SP
6
SP
5
SP
4
SP
2
SP
1
SP
0
SP
3
Echo Canceller A, Sin Peak Detect Register 1
Echo Canceller B, Sin Peak Detect Register 1
ADDRESS = 0Eh READ
ADDRESS = 2Eh READ
These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16-bit 2’s
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low
byte is in Register 1.
SP
SP
Power Reset Value
N/A
7
6
5
4
3
2
1
0
EP
15
EP
14
EP
13
EP
12
EP
10
EP
9
EP
8
EP
11
Echo Canceller A, Error Peak Detect Register 2
Echo Canceller B, Error Peak Detect Register 2
ADDRESS = 11h READ
ADDRESS = 31h READ
Power Reset Value
N/A
7
6
5
4
3
2
1
0
EP
7
EP
6
EP
5
EP
4
EP
2
EP
1
EP
0
EP
3
Echo Canceller A, Error Peak Detect Register 1
Echo Canceller B, Error Peak Detect Register 1
ADDRESS = 10h READ
ADDRESS = 30h READ
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2’s complement
linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in
Register 1.
EP
EP
相關PDF資料 |
PDF描述 |
|---|---|
| MT9123AE | CMOS Dual Voice Echo Canceller |
| MT9123 | Dual Voice Echo Canceller(雙話音回聲消除器) |
| MT9123AP | CMOS Dual Voice Echo Canceller |
| MT9125AE | CMOS Dual ADPCM Transcoder |
| MT9125AP | CMOS Dual ADPCM Transcoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MT9122AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:ECHO CANCELLER CHIP 2CH G.164/G.165/G.711 W/ TONE DETECTION - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DUAL VOICE ECHO CANCELLER W/TD |
| MT9122APR1 | 制造商:Zarlink Semiconductor Inc 功能描述:ECHO CANCELLER CHIP 2CH G.164/G.165/G.711 W/ TONE DETECTION - Tape and Reel |
| MT9123 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Dual Voice Echo Canceller |
| MT9123AE | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.165/G.711 W/OUT TONE DETECTION 28P - Rail/Tube |
| MT9123AE1 | 制造商:Microsemi Corporation 功能描述: |
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