參數(shù)資料
型號: MT9160AN1
廠商: Zarlink Semiconductor Inc.
元件分類: Codec
英文描述: 3 Volt Multi-Featured Codec (MFC)
中文描述: 3伏多精選編解碼器(MFC)中
文件頁數(shù): 8/33頁
文件大?。?/td> 527K
代理商: MT9160AN1
MT91L60/61
Data Sheet
8
Zarlink Semiconductor Inc.
Figure 4 - Audio Gain Partitioning
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
X
X
A
2
A
1
A
0
R/W
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
1)
2)
Delays due to internal processor timing which are transparent.
The MT91L60/L61:latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
3)
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
4)
5)
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1)
3)
4)
5)
1)
2)
3)
4)
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 1
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
D
7
D
0
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
X
X
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1)
3)
4)
1)
2)
3)
4)
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 2
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
R/W
X
A
1
A
0
X
D
7
D
0
1)
2)
Delays due to internal processor timing which are transparent.
The MT91L60/L61: latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
3)
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
4)
5)
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused
5)
X
X
A
2
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