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參數(shù)資料
| 型號(hào)： | MT9161B |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | 5 Volt Multi-Featured Codec (MFC)(5V 多特性編解碼器) |
| 中文描述： | 5伏多功能的編解碼器（MFC）中（5V的多特性編解碼器） |
| 文件頁數(shù)： | 8/30頁 |
| 文件大小： | 154K |
| 代理商： | MT9161B |
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MT9160B/61B
Advance Information
86
DEN:
When 1, ST-BUS D-channel data (1 or 2 bits/frame
depending on the state of the D8 bit) is shifted into/
out of the D-channel (READ/WRITE) register.
When 0, the receive D-channel data (READ) is still
shifted into the proper register while the DSTo
D-channel timeslot and IRQ outputs are tri-stated
(default).
D8:
When 1, D-Channel data is shifted at the rate of 1 bit/
frame (8 kb/s).
When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
frame. By arbitrarily assigning ST-BUS frame n as
the
reference
frame,
microprocessor D-Channel read and write operations
are performed, then:
during
which
the
(a) A microport read of address 04 hex will result in a
byte of data being extracted which is composed of
four di-bits (designated by roman numerals I,II,III,IV).
These di-bits are composed of the two D-Channel
bits received during each of frames n, n-1, n-2 and
n-3. Referring to Fig. 7a: di-bit I is mapped from
frame n-3, di-bit II is mapped from frame n-2, di-bit III
is mapped from frame n-1 and di-bit IV is mapped
from frame n.
The D-Channel read register is not preset to any
particular value on power-up (PWRST) or software
reset (RST).
(b) A microport write to Address 04 hex will result in
a byte of data being loaded which is composed of
four di-bits (designated by roman numerals I, II, III,
IV). These di-bits are destined for the two D-Channel
bits transmitted during each of frames n+1, n+2, n+3,
n+4. Referring to Fig. 7a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is
mapped to frame n+3 and di bit IV is mapped to
frame n+4.
If no new data is written to address 04 hex, the
current
D-channel
register
continuously re-transmitted. The D-Channel write
register is preset to all ones on power-up (PWRST)
or software reset (RST).
contents
will
be
An interrupt output is provided (IRQ) to synchronize
microprocessor access to the D-Channel register
during valid ST-BUS periods only. IRQ will occur
every fourth (eighth in 8 kb/s mode) ST-BUS frame at
the beginning of the third (second in 8 kb/s mode)
ST-BUS bit cell period. The interrupt will be removed
following a microprocessor Read or Write of Address
04 hex or upon encountering the following frames F0i
input, whichever occurs first. To ensure D-Channel
data integrity, microport read/write access to
Address 04 hex must occur before the following
frame pulse. See Figure 7b for timing.
8 kb/s operation expands the interrupt to every eight
frames and processes data one-bit-per-frame.
D-Channel register data is mapped according to
Figure 7c.
Cen - C-Channel
Channel 1 conveys the control/status information for
the Layer 1 transceiver. C-Channel data is
transferred MSB first on the ST-BUS by the
MT9160B/61B. The full 64 kb/s bandwidth is
available and is assigned according to which
transceiver is being used. Consult the data sheet for
the selected transceiver for its C-Channel bit
definitions and order of bit transfer.
When CEN is high, data written to the C-Channel
register
(address
05h)
significant bit first, on DSTo. On power-up reset
(PWRST) or software reset (Rst, address 03h) all
C-Channel bits default to logic high. Receive
C-Channel data (DSTi) is always routed to the read
register regardless of this control bit's logic state.
is
transmitted,
most
When low, data transmission is halted and this
timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels,
respectively. B-channel PCM associated with the
Filter/Codec and transducer audio paths is selected
on an independent basis for the transmit and receive
paths. TxBSel and RxBSel (Control Register 1,
address 03h) are used for this purpose.
If no valid transmit path has been selected then the
timeslot output on DSTo is tri-stated (see PDFDI and
PDDR control bits, Control Register 1 address 03h).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9161BE | 制造商:Microsemi Corporation 功能描述:MULTI-FEATURED CODEC 24SOIC W - Rail/Tube |
| MT9161BN | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT9161BS | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:5 Volt Multi-Featured Codec (MFC) |
| MT9162 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:5 Volt Single Rail Codec |
| MT9162AE | 制造商:Microsemi Corporation 功能描述:CODEC 20PDIP - Rail/Tube |
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