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參數(shù)資料
| 型號： | MT92303 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | 3.3V Quad Interface, Dual Codec(3.3V 四接口雙編解碼器（提供音頻到PCM的接口）) |
| 中文描述： | 3.3四種接口，雙編解碼器（3.3四接口雙編解碼器（提供音頻到的PCM的接口）） |
| 文件頁數(shù)： | 12/34頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MT92303 |
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MT92303
Preliminary Information
12
Figure 13 - SSI Bit Allocation
SC2
SCK
SDR
B2
SDT
B1
B2
B1
B2
B1
Codec 0
Codec 1
B2
B1
status
SDR
SDT
B1
B1
Codec 1
status
Codec 0 disabled, Codec 1 companded
Codec 0 and 1 enabled, both 16-bit linear
SC2
Serial Microport
All MT92303 internal registers are accessed for write
via the serial microport to allow programming of the
device. In addition some registers may be read via
this interface as defined in the ‘Programming and
Registers’ section.
The serial microport is compatible with Intel MCS-51
(mode 0), Motorola SPI (CPOL=0, CPHA=0), and
National Semiconductor Microwire specifications.
Functional waveforms are shown in Figures 14 and
15. Detailed timing diagrams are shown in Figures
20 and 21 in the electrical characteristics section.
The microport consists of a transmit/receive data pin
(DATA1), a receive data pin (DATA2), a chip select
pin (CS) and a synchronous data clock pin (SCLK).
Receive data bits are sampled on the rising edge of
SCLK while transmit data is clocked out on the falling
edge of SCLK.The MT92303 automatically adjusts
its internal timing and pin configuration to conform to
Intel
or
Motorola/National
microport dynamically senses the state of the SCLK
pin each time CS pin becomes active (i.e. high to low
transition). If SCLK pin is high during CS activation,
then Intel mode 0 timing is assumed. In this case
DATA1 pin is defined as a bi-directional (transmit/
receive) serial port and DATA2 is internally
disconnected. If SCLK is low during CS activation,
then Motorola/National timing is assumed and
DATA1 is defined as the data transmit pin while
DATA2 becomes the data receive pin.
requirements.
The
The
processor mode (CPOL=0 and CPHA=0). This
means that during a write to the MT92303 by the
Motorola-type processor, output data from the DATA1
pin must be ignored (by the processor). This also
means that input data on the DATA2 pin is ignored by
the MT92303 during a valid read by the Motorola
processor. All data transfers through the microport
are two bytes long. This requires the transmission of
a Command/Address byte followed by the data byte
to be written to or read from the addressed register.
CS must remain low for the duration of this two-byte
MT92303
supports
Motorola
half-duplex
Pin Name Type
Description
CS
Input Enables serial microport.
Active Low.
SCLK
Input Data clock for serial microport
DATA1
I/O
Motorola/National mode:
DATA1 is output.
Intel mode:
DATA1 is I/O.
DATA2
Input Motorola/National mode:
DATA2 is input.
Intel mode:
DATA2 is not used and must be
tied to VDD or GND
Table 5. Microport Pin Description
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