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| 型號(hào)： | MTA81010-XTI/P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 12/76頁(yè) |
| 文件大小： | 745K |
| 代理商： | MTA81010-XTI/P |
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MTA81010
DS39005D-page 2
1995 Microchip Technology Inc.
MTA81010 PIN DESCRIPTIONS
Name
Function
Description
RA3: RA0
I/O PORT A
4 input/output lines.
RB7: RB0
I/O PORT B
8 input/output lines.
T0CKI
Clock input to TMR0 register
Schmitt Trigger Input.
Clock input to T0CKI register. Must be tied to VSS or VDD if not in
use to avoid unintended entering of test modes and to reduce
current consumption.
MCLR
Master Clear
Schmitt Trigger Input.
A “Low” voltage on this input generates a RESET for the
microcontroller.
A rising voltage triggers the on-chip oscillator start-up timer which
keeps the chip in RESET mode for about 18 ms. This input must be
tied directly, or via a pull-up resistor, to VDD.
OSC1
Oscillator (input)
XT and LP devices:
Input terminal for crystal, ceramic resonator, or external clock
generator.
RC devices:
Driver terminal for external RC combination to establish oscillation.
OSC2/CLKOUT
Oscillator (output)
For XT and LP devices:
Output terminal for crystal and ceramic resonator.
Do not connect any other load to this output.
Leave open if external clock generator is used.
For RC devices:
A CLKOUT signal with a frequency of 1/4 FOSC1 is put out on this
pin.
MCVDD
Power supply
VSS
Ground
SDA
Serial Address/Data I/O
This is a bidirectional pin used to transfer addresses and data into
and data out of the device. It is an open drain terminal.
For normal data transfer SDA is allowed to change only during SCL
low. Changes during SCL high are reserved for indicating the
START and STOP.
SCL
Serial Clock
This input is used to synchronize the data transfer from and to the
device.
WP
Write Protect Input
This pin must be connected to either VSS or SEEVDD.
If tied to VSS, normal memory operation is enabled (read/write the
entire memory 00-7F or 00-FF).
If tied to SEEVDD, WRITE operations are inhibited. The entire
memory will be write-protected. Read operations are not affected.
This feature allows the user to use the 24LC01B as a serial ROM
when WP is enabled (tied to SEEVDD).
SEEVDD
+2.5V to 5.5V Power Supply
N/C
No (internal) Connection
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