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參數(shù)資料
| 型號(hào)： | MTA81010-XTI/P |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 56/76頁 |
| 文件大小： | 745K |
| 代理商： | MTA81010-XTI/P |
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MTA81010
DS39005D-page 6
1995 Microchip Technology Inc.
2.1
MICROCONTROLLER
ARCHITECTURAL DESCRIPTION
2.1.1
HARVARD ARCHITECTURE
The MTA81XXX family contains a, high-speed, fully
static CMOS CPU with EPROM, RAM, and I/O on a
single die.
The architecture is based on a register file concept with
separate bus and memories for data and instructions
(Harvard architecture). The data bus and memory
(RAM) are 8-bits wide while the program bus and
program memory (EPROM) have a width of 12-bits.
This concept allows a simple yet powerful instruction
set designed to emphasize bit, byte and register
operations
under
high
speed
with
overlapping
instruction fetch and execution cycles. That means
that, while one instruction is executed, the following
instruction is already being read from the program
memory. A block diagram of the microcontroller core is
given in Figure 2-2.
2.1.2
CLOCKING SCHEME/INSTRUCTION
CYCLE
The clock input (from pin OSC1) is internally divided by
four to generate four non overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, PC is
incremented every Q1, instruction is fetched from
program memory and latched into instruction register in
Q4. It is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 2-1.
2.1.3
DATA REGISTER FILE
The 8-bit
data bus connects two basic functional
elements together: the Register File composed of
32 addressable 8-bit registers including the I/O Ports,
and an 8-bit wide Arithmetic Logic Unit. The 32 bytes of
RAM are directly addressable (Figure 3-2). Data can
be addressed direct or indirect using the file select
register (f4). Immediate data addressing is supported
by special "literal" instructions which load data from
program memory into the W register.
The register file is divided into two functional groups:
operational registers and general purpose registers.
The operational registers include the Real Time Clock
Counter (T0CKI) register, the Program Counter (PC),
the Status Register, the I/O registers (PORTs), and the
File Select Register. The general purpose registers are
used for data and control information under command
of the instructions.
In addition, special purpose registers
are used to
control the I/O port configuration, and the prescaler
options.
2.1.4
ARITHMETIC/LOGIC UNIT (ALU)
The 8-bit wide ALU contains one temporary working
register (W Register). It performs arithmetic and
Boolean functions between data held in the W Register
and any file register. It also does single operand
operations on either the W register or any file register.
2.1.5
PROGRAM MEMORY
512 words of 12-bit wide on-chip program memory
(EPROM) can be directly addressed (Figure 3-6).
Sequencing of microinstructions is controlled via the
Program Counter (PC) which automatically increments
to
execute
in-line
programs.
Program
control
operations,
supporting
direct,
indirect,
relative
addressing modes, can be performed by Bit Test and
Skip instructions, Call instructions, Jump instructions or
by loading computed addresses into the PC.
In
addition, an on-chip two-level stack is employed to
provide easy to use subroutine nesting.
FIGURE 2-2:
CLOCKS/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
(Program counter)
OSC2/CLKOUT
(RC mode)
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
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