參數(shù)資料
型號(hào)： MTA81010-XTI/P
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28
封裝： PLASTIC, DIP-28
文件頁(yè)數(shù)： 75/76頁(yè)
文件大?。?/td> 745K
代理商： MTA81010-XTI/P
MTA81010
DS39005D-page 8
1995 Microchip Technology Inc.
FIGURE 3-3:
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALE
FIGURE 3-4:
TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC-1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
Instruction
Fetch
TMR0
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
T0
T0+1
T0+2
NT0
NT0+1
NT0+2
T0
MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 2
Instruction
Executed
PC-1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
Instruction
Fetch
TMR0
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
T0
NT0+1
MOVWF TMR0 MOVF TMR0,WMOVF TMR0,W MOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
T0+1
NT0
Instruction
Execute
3.1.1
USING TMR0 WITH EXTERNAL CLOCK
When an external clock input is used for TMR0, it must
meet certain requirements to be able to synchronize
with the internal phase clock (TOSC). Also, there is a
delay in the actual incrementing of TMR0 after
synchronization.
3.1.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output.
Synchronizing
T0CKI with the internal phase clocks requires sampling
the prescaler output on the Q2 and Q4 cycles of the
internal phase clocks (Figure 3-5). Therefore, it is nec-
essary for T0CKI to be high for at least 2 TOSC (plus a
small RC delay) and low for at least 2 TOSC (plus a
small RC delay). Refer to the appropriate electrical
specification table.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler to ensure that the prescaler output is
symmetrical. For the external clock to meet the
sampling requirement, the ripple counter must be taken
into account. Therefore, it is necessary for T0CKI to
have a period of at least 4 TOSC (plus a small RC delay)
divided by the prescaler value. The only limitation on
T0CKI high and low time is that they are greater than
the minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the appropriate electrical
specification section.
3.1.1.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 mod-
ule is actually incremented. Figure 3-5 shows the delay
from the external clock edge to the timer incrementing.
3.1.2
PRESCALER
An 8-bit counter is available as a prescaler for the
TMR0 module, or as a post-scaler for the Watchdog
Timer, (Section 3.1.1.2). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet. Note that there is only one prescaler available
which is mutually exclusive between the TMR0 module
and the Watchdog Timer. Thus, a prescaler assignment
for the TMR0 module means that there is no prescaler
for the Watchdog Timer, and vice-versa.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the TMR0 module, all instructions
writing to the TMR0 module (e.g., CLRF 1, MOVWF 1,
BSF
1,x
....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler
along with
the Watchdog
Timer. The
prescaler is neither readable nor writable. On a RESET,
the prescaler contains all '0's.
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