參數(shù)資料
型號(hào)： MTA81010T-XT/SO
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
封裝： 0.300 INCH, SOIC-28
文件頁數(shù)： 16/76頁
文件大小： 745K
代理商： MTA81010T-XT/SO
1995 Microchip Technology Inc.
DS39005D-page 23
MTA81010
7.0
RESET CONDITION
A RESET can be caused by applying power to the chip
(power-up), pulling the MCLR input "low", or by a
Watchdog timer time-out. The device will stay in
RESET as long as the oscillator start-up timer (OST) is
active or the MCLR input is "low."
The oscillator start-up timer is activated as soon as
MCLR input is sensed to be high. This implies that in
case of power on reset with MCLR tied to VDD the OST
starts from power-up. In case of WDT time-out, it will
start at the end of the time-out (since MCLR is high). In
case of MCLR reset, the OST will start when MCLR
goes high. The nominal OST time-out period is 18 ms.
See Section 12.0 for detailed information on OST and
power on reset.
During a RESET condition the state of the PIC16C54 is
defined as:
The oscillator is running, or will be started
(power-up or wake-up from SLEEP).
All I/O port pins (RA3:RA0, RB7:RB0) are put into
the high-impedance state by setting the "TRIS"
registers to all "ones" (= input mode).
The Program Counter is set to all "ones".
The OPTION register is set to all "ones".
The Watchdog Timer and its prescaler are
cleared.
The upper three bits (page select bits) in the
Status Register (f3) are cleared to "zero."
"RC" devices only: The "CLKOUT" signal on the
OSC2 pin is held at a "low" level.
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