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參數(shù)資料
| 型號： | MTA81010T-XT/SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 29/76頁 |
| 文件大?。?/td> | 745K |
| 代理商： | MTA81010T-XT/SO |
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1995 Microchip Technology Inc.
DS39005D-page 35
MTA81010
12.0
OSCILLATOR START-UP TIMER
(OST)
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. An on-chip oscillator start-
up timer is provided which keeps the device in a
RESET for approximately 18 ms after the voltage on
the MCLR pin has reached a logic high (VIHMC) level.
Thus, external RC networks connected to the MCLR
input are not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications.
The OST will also be triggered upon a watchdog timer
time-out. This is particularly important for applications
using the WDT to awake the MTA81010 from SLEEP
mode automatically.
The OST is not adequate for low frequency crystals
which require much longer than 18 ms to start up and
stabilize.
12.1
Power On Reset (POR)
The MTA81010 incorporates an on-chip Power On
Reset (POR) circuitry which provides internal chip reset
for most power-up situations. To use this feature the
user merely needs to tie MCLR pin to MCVDD. A sim-
plified block diagram of the on-chip power on reset cir-
cuit is shown in Figure 12-4. The power on reset circuit
and the oscillator start-up timer circuit are closely
related. On power-up the reset latch is set and the
start-up timer (Figure 12-4) is reset. The start-up timer
begins counting once it detects MCLR to be high. After
the time-out period, which is typically 18 ms, it will reset
the reset-latch and thus end the on-chip reset signal.
Figure 12-5
and
Figure 12-6
are
two
power-up
situations with relatively fast rise time on MCVDD. In
Figure 12-5, MCVDD is allowed to rise and stabilize
before bringing MCLR high. The chip will actually come
out of reset TOST ms after MCLR goes high. In
Figure 12-6, the on chip power-on reset feature is
being utilized (MCLR and MCVDD are tied together).
The MCVDD is stable before the start-up timer times out
and there is no problem in getting a proper reset.
Figure 12-7 depicts a potentially problematic situation
where MCVDD rises too slowly. In this situation, when
the start-up timer times out, MCVDD has not reached
the MCVDD (minimum) value and the chip is therefore
not guaranteed to function correctly.
To
summarize,
the
on-chip
power
on
reset
is
guaranteed to work if the rate of rise of MCVDD is no
slower than 0.05 V/ms. It is also necessary that the
MCVDD starts from 0V. The on-chip power on reset is
also not adequate for low frequency crystals which
require much longer than 18 ms to start up and
stabilize. For such situations, we recommend that
external RC circuits are used for longer power on reset.
FIGURE 12-1: EXTERNAL POWER ON
RESET CIRCUIT
FIGURE 12-2: BROWN OUT PROTECTION
CIRCUIT
FIGURE 12-3: BROWN OUT PROTECTION
CIRCUIT
Note:
1. External power-on reset circuit is required only if
VDD power-up slope is too slow. The diode D
helps discharge the capacitor quickly when VDD
powers down.
2. R < 40 k
is recommended to make sure that
voltage drop across R does not exceed 0.2V (max
leakage current spec on MCLR pin is 5
A). A
larger voltage drop will degrade VIH level on
MCLR pin.
3. R1 = 100
to 1 k will limit any current flowing
into MCLR from external capacitor C in the event
of MCLR pin breakdown due to ESD or EOS.
C
R1
R
D
VDD
MCLR
MTA81010
Note:
1.
This circuit will activate reset when VDD goes
below (Vz + 0.7V) where Vz = Zener voltage.
VDD
33k
10k
40k
VDD
MCLR
MTA81010
Note:
1.
This brown circuit is less expensive, albeit
less accurate. Transistor Q1 turns off when
VDD is below a certain level such that:
VDD
R1
R1 + R2
= 0.7V.
VDD
R2
R3
VDD
MCLR
MTA81010
R1
Q1
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